大家来看看，关于FSM的一个问题！

liyun022 · 发表于 2006-9-13 00:10:12

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　　大家主要看看状态编码，功能不用管它！
　　关于FSM中的状态编码one-hot,以前我是用写法一，以为这样就是one-hot了。后来看资料，发现资料上的是写法二，汗！
　　可是我把写法一跟写法二拿到synplify8.2听综合后发现网表是一模一样的！！！这是怎么回事？大家发表一下自己的看法。
　　第一种写法有些什么问题呢？是不是这样也是可以的？还是说这样不好，只不过,在这里syplify经过优化，使两种写法的结果一样了？
写法一：
　　//3 always style
module ASM5(CLK, Rst_n, N, D, Dispense) ;
output Dispense ;
input  CLK ;
input  Rst_n ;
input  N ;
input  D ;

parameter Idle = 4'b0001 ,
      State5  = 4'b0010 ,
      State10 = 4'b0100 ,
      State15 = 4'b1000 ;

reg Dispense ;
reg [3:0] cur_state, next_state ;

always @(posedge CLK or negedge Rst_n)
if(!Rst_n)
      cur_state <= Idle ;
else
      cur_state <= next_state ;
always @(cur_state or N or D)
begin
case(cur_state)
      Idle:
         if(N)
            next_state = State5 ;
         else if(D)
            next_state = State10 ;
         else
            next_state = Idle ;
      State5:
         if(N)
            next_state = State10 ;
         else if(D)
            next_state = State15 ;
         else
            next_state = State5 ;
      State10:
         if(N || D)
            next_state = State15 ;
         else
            next_state = State10 ;
      State15:
         next_state = Idle ;
      default:
         next_state = Idle ;
   endcase
end

always @(posedge CLK or negedge Rst_n)
if(!Rst_n)
      Dispense <= 1'b0 ;
else if(cur_state == State15)
      Dispense <= 1'b1 ;
else
      Dispense <= 1'b0 ;
endmodule

写法二：
　　//3 always style
//state encoded by one-hot
module ASM4(CLK, Rst_n, N, D, Dispense) ;
output Dispense ;
input  CLK ;
input  Rst_n ;
input  N ;
input  D ;

parameter Idle = 0 ,
      State5  = 1 ,
      State10 = 2 ,
      State15 = 3 ;

reg Dispense ;
reg [3:0] cur_state, next_state ;

always @(posedge CLK or negedge Rst_n)
if(!Rst_n)
      cur_state <= 4'b0001 ;
else
      cur_state <= next_state ;
always @(cur_state or N or D)
begin
next_state = 4'b0 ;
case(1'b1)
      cur_state[Idle]:
         if(N)
            next_state[State5] = 1'b1 ;
         else if(D)
            next_state[State10] = 1'b1 ;
         else
            next_state[Idle] = 1'b1 ;
      cur_state[State5]:
         if(N)
            next_state[State10] = 1'b1 ;
         else if(D)
            next_state[State15] = 1'b1 ;
         else
            next_state[State5] = 1'b1 ;
      cur_state[State10]:
         if(N || D)
            next_state[State15] = 1'b1 ;
         else
            next_state[State10] = 1'b1 ;
      cur_state[State15]:
         next_state[Idle] = 1'b1 ;
      default:
         next_state[Idle] = 1'b1 ;
   endcase
end

always @(posedge CLK or negedge Rst_n)
if(!Rst_n)
      Dispense <= 1'b0 ;
else if(cur_state[State15])
      Dispense <= 1'b1 ;
else
      Dispense <= 1'b0 ;
endmodule

　　

[ 本帖最后由 liyun022 于 2006-9-13 00:20 编辑 ]