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Preface
I first became familiar with PLLs by
working for National Semiconductor as an
applications engineer. While supporting
customers, I noticed that there were many
repeat questions. Instead of creating the
same response over and over, it made more
sense to create a document, worksheet, or
program to address these recurring questions
in greater detail and just re-send the file.
From all of these documents, worksheets,
and programs, this book was born.
Many questions concerning PLLs can be
answered through a greater understanding of
the problem and the mathematics involved.
By approaching problems in a rigorous
mathematical way one gains a greater level
of understanding, a greater level of
satisfaction, and the ability to apply the
concepts learned to other problems.
Many of the formulas that are commonly
used for PLL design and simulation contain
gross approximations with no or little
justification of how they were derived. Others are rigorously derived, but from outdated
textbooks that make assumptions not true of the PLL systems today. It is therefore no
surprise that there are so many rules of thumb to be born which yield unreliable results.
Another fault of these formulas is that many of them have not been compared to measured
data to ensure that they account for all relevant factors.
There is also the other approach, not trusting formulas enough and relying on only measured
results. The fault with this is that many great insights are lost and it is difficult to learn and
grow in PLL knowledge this way. Furthermore, by knowing what a result should
theoretically be, it makes it easier to spot and diagnose problems with a PLL circuit. This
book takes a unique approach to PLL design by combining rigorous mathematical
derivations for formulas with actual measured data. When there is agreement between these
two, then one can feel much more confident with the results.
The purpose of writing a third edition is to add significant details and understanding to what
was in the second edition. This includes insights into delta sigma PLLs, fractional spurs,
phase noise, lock time, and loop filter design. |
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发表于 2004-3-25 17:30:04
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