virtuoso新建verilog cellview报错

bynnz

自己写的verilog   extract failed，没法生成symbol

                               
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同时virtuoso的终端里报错 14: failed to connect to all addresses   没查到这是什么原因
在命令行用cmd命令运行xrun能够编译.v文件 但是virtuoso里没法导入

[bynnz@xunipc verilogA_Micro_Ring7.23.2025]$ xrun -clean verilog.v
TOOL:        xrun        22.09-s005: Started on Sep 04, 2025 at 17:23:09 CST
xrun: 22.09-s005: (c) Copyright 1995-2023 Cadence Design Systems, Inc.
xrun: *N,CLEAN: Removing existing directory ./xcelium.d.
file: verilog.v
        module worklib.fsm_controller:v
                errors: 0, warnings: 0
                Caching library 'worklib' ....... Done
        Elaborating the design hierarchy:
        Top level design units:
                fsm_controller
        Building instance overlay tables: .................... Done
        Generating native compiled code:
                worklib.fsm_controller:v <0x6e79a163>
                        streams:   0, words:     0
        Building instance specific data structures.
        Loading native compiled code:     .................... Done
        Design hierarchy summary:
                                 Instances  Unique
                Modules:                 1       1
                Registers:               8       8
                Always blocks:           4       4
                Simulation timescale:  1ps
        Writing initial simulation snapshot: worklib.fsm_controller:v
Loading snapshot worklib.fsm_controller:v .................... Done
xcelium> source /opt/cadence/xcelium_2209_005/tools/xcelium/files/xmsimrc
xcelium> run
xmsim: *W,RNQUIE: Simulation is complete.
xcelium> exit
TOOL:        xrun        22.09-s005: Exiting on Sep 04, 2025 at 17:23:09 CST  (total: 00:00:00)


有没有大佬教教是哪里不对

bynnz

新建verilog cell的报错是
(TE-4223): Extracting cellview '8MRMs fsm_controller functional' ...
ERROR (TIVLOG-5006): Unable to initialize the parser (visadev) for the design '8MRMs fsm_controller functional'.
ERROR (TIVLOG-34): Unable to parse the file, '/home/bynnz/PIC-OIO-test/verilogA_Micro_Ring7.23.2025/8MRMs/fsm_controller/functional/verilog.v', for cellview '(8MRMs fsm_controller functional)'.

ERROR (TI-7001): Cannot load the connectivity information for cellview '8MRMs/fsm_controller/functional' in text file
'/home/bynnz/PIC-OIO-test/verilogA_Micro_Ring7.23.2025/8MRMs/fsm_controller/functional/verilog.v'.
Verilog *E,PARSEERR: Either there are parsing errors or cell fsm_controller
                    is not found in /home/bynnz/PIC-OIO-test/verilogA_Micro_Ring7.23.2025/8MRMs/fsm_controller/functional/verilog.v
                    file.
*WARNING* (TE-4309): Extract failed for cellview '8MRMs fsm_controller functional'