hier DFT OCC in top level

wang_uestc

如果顶层某些clock同时control 多个physical core，OCC inserted in TOP level，core level transition pattern可以通过NCP产生，可是如何retargetting to TOP呢？
TOP level OCC/occ_control/ShiftReg/FF_reg* 控制值如何做？

Tessent UG mentioned：


If the clock controller is outside the core, it must have been programmed statically
during test_setup to deliver the same clock sequence during the capture phase of every
pattern. During core-level ATPG, the clocking at the core boundary must be enforced by
defining an NCP. In addition, any unconstrained pins on the core boundary must have
the is_excluded_from_isolation_constraints attribute set; otherwise, the tool constrains
them to X.



Google got：

[size=1.1875]In the case of the hierarchical test methodology, it is easiest if the OCCs are all located within each block. This way, all clock programming in ShiftReg is contained in each block-level scan pattern. Any set of block-level scan patterns with any type of clocking are completely plug-and-play and can be merged with any other block patterns at the top level of the design. OCCs in the blocks are the most flexible practice.

[size=1.1875]If it isn't possible to put OCCs within blocks, then hierarchical test and pattern retargeting to the top level design is still possible, but it is a little more complicated. The top-level OCC programming can't be embedded with the OCC ShiftReg loaded as part of the scan patterns because the scan patterns are created without the presence of the top-level design. Instead, the strategy is to set up the OCC to perform a repeated clock waveform for a group of patterns. The top-level OCC will not have the ShiftReg located with any scan chains, but as a test data register that can be statically loaded during test mode initialization. Then a set of block-level patterns with that same capture cycle clock waveform within each can be retargeted to the top level.

wang_uestc

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