FinFet current mirror design needed

onepound

Guys I cant make  an accurated cascode current mirror with FinFets

What is the trick here?
With a 16nm process the maximum gate lenght is 30nm and whatever I do the mirror is really poor.


Any sugestions?

kwkam

cascaded the MOSFET

zhanweisu33

self-bias cascode mirror  

onepound

I was using 1.8V FinFet and rubbish cm but 0.8V FinFet are fine - don't know why?

peterlin2010

1. Basic FinFET Current Mirror Topology

A basic current mirror typically consists of two matched NMOS or PMOS transistors. In FinFETs, the same concept applies, but the current is quantized by the number of fins, not by W/L.

2. FinFET Design Considerations

Unlike planar CMOS, FinFETs don’t use W/L ratios. Instead, the drive strength is controlled by the number of fins:

• I ∝ N_fins × (L_eff)
  • NfinsN_{fins}Nfins​: Number of fins
  • LeffL_{eff}Leff​: Effective channel length (fixed for a given process)
    
    
  
  

Key Parameters:ParameterFinFET
Width (W)W=Nfins×WfinW = N_{fins} × W_{fin}W=Nfins​×Wfin​
Gate Length (L)Defined by technology (e.g., 16nm, 7nm)
Drive StrengthControlled by number of fins
MatchingImproves with layout symmetry and common centroid techniques


. SPICE Simulation Tips

If you're simulating:

• Use FinFET PDK (e.g., from Synopsys, Cadence, or open-source like ASAP7)
• Use models that reflect quantized fins
• Sweep input current (I_ref) and observe I_out
• Perform Monte Carlo analysis for mismatch effects
  
  

3. Design StepsStep 1: Choose Technology Parameters

• Technology node: e.g., 7nm or 14nm FinFET
• Supply voltage: e.g., 0.7V – 1.0V
• Fin width WfinW_{fin}Wfin​: Fixed by tech (e.g., ~7 nm)
• Fin height HfinH_{fin}Hfin​: Also fixed
  
  

Step 2: Select Number of Fins

• Choose N_fins = 2 or more for both M1 and M2
• Match the number of fins for good current mirroring
  
  

Step 3: Biasing Current

• Apply reference current (I_ref) via a current source or resistor to M1
• Ensure M1 is in saturation
  
  

Step 4: Layout Considerations

• Use common-centroid layout
• Match lengths of interconnects (especially gate and drain)
• Use dummy fins at the edges to improve symmetry
  
  

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✅ 4. Example (7nm FinFET)

Assume:

• Supply voltage: 0.8V
• Target I_ref: 10 µA
• Device threshold voltage VthV_{th}Vth​: ~0.3V
  
  

Design Steps:

• Use NMOS FinFETs
• Select 2 fins per transistor (adjust based on sizing/simulation)
• Connect gates and M1 drain together
• Use current source or diode-connected load to generate I_ref
  
  

zhanweisu33

i think there is sth wrong with ur PDK,
the maximum L of 16nm 0.8 FET also is not 30nm only

YyuanRTs

It is recommended to use series mos to get larger effective channel length, which also be called stack or self-cascode.
Also, the channel length limitation is only active when length is small. Try to use larger number and it will be free to set length.

onepound

okay thanks guys the 0.8V FinFet is fine but the 1.8V standard Vt FinFet has poor current mirroring what ever I try. Maybe the 1.8V FinFet are just poor?

nanke

多串几个就好了，finfet gm比平面工艺强。