Async SAR ADC Full Swing question

mitchell0001

Hi, All:

       I design a differential Asyn. SAR, the input must increase to -Vref+deltaV or Vref-deltaV. The first code and final code can be decision.
Does anybody meet the same problems ?  And any solution for this behavior.

PS. I use boostrap Switch (NMOS)

Thanks all.

chungming

this is inevitab, if you use top plate sampling. I remember that bottom-plate sampling has no such problem.

mitchell0001

I used the Top plate sampling, any other solution ?

chungming

   

mitchell0001 发表于 2025-7-28 08:39
I used the Top plate sampling, any other solution ?

in my limited experience, use PGA in front of ADC and do the calibration before the using. Or you can change the refernece votlage by calibration.

Other than that, using bottom-plate sampling is a good way to go.

abab1394

the top plate sampling has gain error by the parasitic cap at the top plate.

mitchell0001

bottom-plate sampling !!!
Async. SAR ?  Any paper or document ?

彭盛輝

你可以看你DAC code 都是1時的電壓是多少~~~