AEC-Q100-002E协议中关于Low Parasitic Tester (LPT) HBM stress 例外处理问题

zhangyang370281

AEC-Q100-002E协议中关于HBM测试中一些例外如下表述：
其中关于 Low Parasitic Tester (LPT)  HBM stress为什么需要做例外处理，从描述来看Low Parasitic Tester (LPT)  HBM stress不需要按照JS-001 Table 2B，可以按照JS-001 Table 2A来（测试压力明显变小），
问题为什么“Low Parasitic Tester (LPT)  HBM stress”要做上述例外处理，有高人能解答一下吗？

二，Pin Stress Combinations

4.1 Devices with six (6) pins or less shall be tested with all possible pin pair combinations (one pin connected to terminal A, another pin connected to terminal B) regardless of pin name or function.

4.2 HBM stress for AEC Q100 shall be initially done using JS-001 Table 2B, with the following exceptions:

a. HBM stress using a Low Parasitic Tester (LPT) (see Section 4.3 below)

b. If a tester artifact is deemed to cause a false HBM failure, options contained within JS-001 Table 2A may be used. （tester的原因导致的fail，也可以转化为table 2A）

c. If a failure is deemed to be caused by cumulative stress, options contained within JS-001 Table 2A may be used. （如果累积fail出现，可以转化为table 2A）

4.3 AEC Q100 stress using a Low Parasitic Tester (LPT), such as a Two Pin HBM Tester.

a. Connectivity for each stress combination shall be verified. Refer to JS-001 Section 5.6.2 (“Non Relay Testers”).

b. Stress may use the Non-Supply to Non-Supply stress method found in JS-001 Table 2A (i.e., Pin combination N+1).

c. In addition to the Coupled Non-Supply Pin Pairs, adjacent Non-Supply pins on the die shall be stressed in two-pin mode.

d. Options outlined in JS-001 Section 6.6 (“HBM Stressing with a Low Parasitic Simulator”) related to LPT HBM testers may be used.

IC_Spark

LPT一般是Two pin tester, 效率很低，按照table 2a可以少打一些组合，感觉像是为了提高测试效率吧

zhangyang370281

   

IC_Spark 发表于 2025-7-15 14:44
LPT一般是Two pin tester, 效率很低，按照table 2a可以少打一些组合，感觉像是为了提高测试效率吧
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table 2a 主要是信号组合要少很多，主要不太明白为啥Two pin tester 就可以呢？还是因为Two pin tester测试结果更精准，relay 矩阵的tester 有较大的wire寄生，可能导致结果不够准确