xcelium problem

ajay.rampelli

xcelium problem while simulation

powertoy

你倒是把下面两个log文件的内容贴出来啊

ajay.rampelli

these are the files
can any one tell me what to do

ajay.rampelli

the two files are

powertoy

csi-xmsim - CSI: Command line:
xmsim
    -f /home/hxxxxxx/Desktop/counter_design_database_45nm/simulation/xcelium.d/run.lnx8664.23.03.d/hxxxxxx_3945/xmsim.args
        -gui
        -MESSAGES
        +EMGRLOG xrun.log
        -XLSTIME 1732691122
        -XLKEEP
        -XLMODE ./xcelium.d/run.lnx8664.23.03.d
        -RUNMODE
        -CDSLIB ./xcelium.d/run.lnx8664.23.03.d/cds.lib
        -HDLVAR ./xcelium.d/run.lnx8664.23.03.d/hdl.var
        -XLNAME xrun
        -XLVERSION TOOL:        xrun(64)        23.03-s002
        -XLNAME ./xcelium.d/run.lnx8664.23.03.d/hxxxxxx_3945
    -CHECK_VERSION TOOL:        xrun(64)        23.03-s002
    -LOG_FD 4
    -LOG_FD_NAME xrun.log
    -cmdnopsim
    -runlock /home/hxxxxxx/Desktop/counter_design_database_45nm/simulation/xcelium.d/run.lnx8664.23.03.d/.xmlib.lock
    -runscratch /home/hxxxxxxx/Desktop/counter_design_database_45nm/simulation/xcelium.d/run.lnx8664.23.03.d/hxxxxxx_3945

csi-xmsim - CSI: *F,INTERR: INTERNAL EXCEPTION
Observed simulation time : 0 FS + 0
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
  TOOL:        xmsim(64)        23.03-s002
  HOSTNAME: hxxxxxx
  OPERATING SYSTEM: Linux 4.18.0-553.22.1.el8_10.x86_64 #1 SMP Tue Sep 24 05:16:59 EDT 2024 x86_64
  MESSAGE: T(0): sv_seghandler - trapno -1 addr(0x6f581ec)
        Stream rts_xfer
-----------------------------------------------------------------

csi-xmsim - CSI: Cadence Support Investigation, recording details
External Code in function: <unavailable> offset -65515
External Code in function: <unavailable> offset -65536
Verilog Syntax Tree: indexed vector type (VST_T_INDEXED_VEC) in module worklib.counter_test:v (VST)
        Scope: counter_test
        Decompile: logic
Verilog Syntax Tree: module declaration (VST_D_MODULE) in module worklib.counter_test:v (VST)
        File: /home/hxxxxxx/Desktop/counter_design_database_45nm/simulation/counter_test.v, line 1, position 18
        Scope: counter_test
        Decompile: counter_test
        Source  : module counter_test;
        Position:                   ^
Simulator Snap Shot: gd (SSS_GD) in snapshot worklib.counter_test:v (SSS)
Verilog Syntax Tree: register declaration (VST_D_REG) in module worklib.counter_test:v (VST)
        File: /home/hxxxxxx/Desktop/counter_design_database_45nm/simulation/counter_test.v, line 2, position 11
        Scope: counter_test
        Decompile: reg rst
        Source  : reg clk, rst;
        Position:            ^
Verilog Syntax Tree: logic type (VST_T_LOGIC) in module worklib.counter_test:v (VST)
        Decompile: reg
Verilog Syntax Tree: logic type (VST_T_LOGIC) in module worklib.counter_test:v (VST)
        Decompile: logic
Intermediate File: string (IF_STRING) in module worklib.counter_test:v (VST)
        Decompile: counter_test
Intermediate File: string (IF_STRING) in module worklib.counter_test:v (VST)
        Decompile: rst
Intermediate File: root (IF_ROOT) in module worklib.counter_test:v (VST)
Simulator Snap Shot: root (SSS_ROOT) in snapshot worklib.counter_test:v (SSS)
Simulator Snap Shot: top level instance (SSS_TLI) in snapshot worklib.counter_test:v (SSS)
External Code in function: <unavailable> offset -65521
External Code in function: <unavailable> offset -65535
csi-xmsim - CSI: investigation complete took 0.012 secs, send this file to Cadence Support

powertoy

看不懂这个触及到我的知识盲区，帮你顶一下

powertoy

xcelium 的 checkSysConf pass了么

cotonier

有没有跑成功过？