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https://dl.acm.org/doi/10.1145/3649476.3660386
The increasing complexity and integration of diverse components in modern System-on-Chip (SoC) designs make them susceptible to a range of attacks. Unfortunately, a substantial disjunction persists between the sophisticated architectures of the SoCs and Design Verification (DV) techniques to detect such vulnerabilities. Recently, Hardware fuzzing, inspired by software testing, has been gaining attention for its efficient bug-detection capabilities in SoC designs. Coverage metrics serve as a pivotal tool in assessing the efficacy of fuzzing techniques by gauging the extent to which the Design Under Test (DUT) design space is explored during the verification process. This paper endeavors to delve into various hardware coverage metrics, encompassing branch, statement, Finite State Machine (FSM), line, and expression coverage, in order to elucidate both the merits and demerits of existing hardware fuzzing methodologies. Furthermore, it seeks to explore how these coverage metrics can be harnessed to bolster the efficacy of hardware fuzzing, thereby augmenting bug detection rates and streamlining testing endeavors. This work provides an analysis on different coverage metrics that could be utilized and the impact of it on the overall design coverage for various IP blocks and CPU designs.
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