锁相环的LOCK侦测模块，有VerilogA代码或者文章参考吗。

uzljuljz

头疼。

ethanchung

`include "disciplines.vams"  module pll_lock_detector(input phase_difference, output reg lock);      // Parameters     parameter real threshold = 0.1;  // Threshold for determining lock     parameter real check_time = 1e-6; // Time window to check for lock     parameter real hysteresis = 0.05; // Hysteresis for lock determination      // Internal signals     real phase_diff_integrated;     real time_count;      analog begin         @(initial_step) begin             phase_diff_integrated = 0;             time_count = 0;             lock = 0;         end          // Integrate phase difference over time         phase_diff_integrated = phase_diff_integrated + abs(phase_difference) * `dt;         time_count = time_count + `dt;          // Check if phase difference is within threshold         if (time_count >= check_time) begin             if (phase_diff_integrated <= threshold) begin                 lock = 1;             end else if (phase_diff_integrated >= threshold + hysteresis) begin                 lock = 0;             end             // Reset integration and time counter             phase_diff_integrated = 0;             time_count = 0;         end     end endmodule

ethanchung

`include "disciplines.vams"

module pll_lock_detector(input phase_difference, output reg lock);

    // Parameters
    parameter real threshold = 0.1;  // Threshold for determining lock
    parameter real check_time = 1e-6; // Time window to check for lock
    parameter real hysteresis = 0.05; // Hysteresis for lock determination

    // Internal signals
    real phase_diff_integrated;
    real time_count;

    analog begin
        @(initial_step) begin
            phase_diff_integrated = 0;
            time_count = 0;
            lock = 0;
        end

        // Integrate phase difference over time
        phase_diff_integrated = phase_diff_integrated + abs(phase_difference) * `dt;
        time_count = time_count + `dt;

        // Check if phase difference is within threshold
        if (time_count >= check_time) begin
            if (phase_diff_integrated <= threshold) begin
                lock = 1;
            end else if (phase_diff_integrated >= threshold + hysteresis) begin
                lock = 0;
            end
            // Reset integration and time counter
            phase_diff_integrated = 0;
            time_count = 0;
        end
    end
endmodule
In this code:

phase_difference: The input signal representing the phase difference between the reference signal and the output signal of the PLL.

lock: The output signal indicating whether the PLL is locked or not.

threshold: The phase difference threshold used to determine if the PLL is locked.

check_time: The time window over which the phase difference is integrated.

hysteresis: The additional threshold margin to prevent oscillation around the lock state.

This lock detector works by integrating the absolute phase difference over a specified time window and comparing it against a threshold. If the integrated phase difference is below the threshold, it indicates that the PLL is locked. The hysteresis parameter helps prevent the lock signal from rapidly toggling due to small fluctuations.

ethanchung

`include "disciplines.vams"

module pll_lock_detector(input phase_difference, output reg lock);

    // Parameters
    parameter real threshold = 0.1;  // Threshold for determining lock
    parameter real check_time = 1e-6; // Time window to check for lock
    parameter real hysteresis = 0.05; // Hysteresis for lock determination

    // Internal signals
    real phase_diff_integrated;
    real time_count;

    analog begin
        @(initial_step) begin
            phase_diff_integrated = 0;
            time_count = 0;
            lock = 0;
        end

        // Integrate phase difference over time
        phase_diff_integrated = phase_diff_integrated + abs(phase_difference) * `dt;
        time_count = time_count + `dt;

        // Check if phase difference is within threshold
        if (time_count >= check_time) begin
            if (phase_diff_integrated <= threshold) begin
                lock = 1;
            end else if (phase_diff_integrated >= threshold + hysteresis) begin
                lock = 0;
            end
            // Reset integration and time counter
            phase_diff_integrated = 0;
            time_count = 0;
        end
    end
endmodule

In this code:

phase_difference: The input signal representing the phase difference between the reference signal and the output signal of the PLL.

lock: The output signal indicating whether the PLL is locked or not.

threshold: The phase difference threshold used to determine if the PLL is locked.

check_time: The time window over which the phase difference is integrated.

hysteresis: The additional threshold margin to prevent oscillation around the lock state.

This lock detector works by integrating the absolute phase difference over a specified time window and comparing it against a threshold. If the integrated phase difference is below the threshold, it indicates that the PLL is locked. The hysteresis parameter helps prevent the lock signal from rapidly toggling due to small fluctuations.

xuwenwei

有吗 ？  只有看一些datasheet上有描述，同求

uzljuljz

感谢

uzljuljz

ethanchung 发表于 2024-10-31 12:54
`include "disciplines.vams"

module pll_lock_detector(input phase_difference, output reg lock);

好的，感谢~

uzljuljz

实测不能运行。。。