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事情是这样的,在做pattern retargeting的流程,在生成core级retargeting pattern的时候,其中某个core级无法生成retargeting pattern,并报出有R7故障,说该模块的时钟端口并不是可控的,请问这是为什么呢,这个时钟端口明明就是很普通的时钟端口,而且没有什么修复的思路,求求有没有懂的大神可以指点迷津,求求了
故障log文件内容如下:
/home/jjt/install/mentor/tessent_2023_1/bin/tessent -shell -dofile 3_modulator_edt_atpg.tcl -log 3_patret.log -replace
// Tessent Shell 2023.1 Fri Feb 17 22:27:00 GMT 2023
// Unpublished work. Copyright 2023 Siemens
//
// This material contains trade secrets or otherwise confidential
// information owned by Siemens Industry Software Inc. or its affiliates
// (collectively, "SISW"), or its licensors. Access to and use of this
// information is strictly limited as set forth in the Customer's
// applicable agreements with SISW.
//
// Siemens software executing under x86-64 Linux on Thu Oct 24 17:10:41 CST 2024.
// 64 bit version
// Host: localhost.localdomain (4 x 2.1 GHz, 3770 MB RAM, 3967 MB Swap)
//
// command: set_context patterns -scan
// command: read_verilog design_edt_module_edt_top_gate.v
// command: read_cell_library /home/jjt/chirp_ijtag/lib/tcb013ghp.mdt
// Reading DFT Library file /home/jjt/chirp_ijtag/lib/tcb013ghp.mdt
// Finished reading file /home/jjt/chirp_ijtag/lib/tcb013ghp.mdt
// command: set_current_mode -type internal
// Note: Mode name was not specified. Defaulting to 'internal' to match the specified type.
// command: report_clocks
// Command 'report_clocks' requires an elaborated design. Automatically elaborating the design ...
// Note: Top design is 'delta_sigma_modulator_edt_top'.
// Warning: 1708 cases: Unused net in DFT library model
// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings
// Design elaboration successful.
// No clocks have been defined.
// command: add_input_constraints scan_enable -C1
// command: add_input_constraints test_mode -C1
// command: add_input_constraints rst_n -C1
// command: analyze_control_signals -auto_fix
// Warning: Rule FN1 violation occurs 4 times
// Warning: Rule FN4 violation occurs 117 times
// Flattening process completed, cell instances=287, gates=1010, PIs=32, POs=5, CPU time=0.01 sec.
// ---------------------------------------------------------------------------
// Begin circuit learning analyses.
// --------------------------------
// Learning completed, CPU time=0.00 sec.
// ---------------------------------------------------------------------------
// Begin control signals identification analysis.
// ---------------------------------------------------------------------------
// Identified 2 clock control primary inputs.
// '/clk' (1) with off-state = 0.
// '/edt_clock' (29) with off-state = 0.
// Identified 0 set control primary inputs.
// Identified 0 reset control primary inputs.
// Identified 0 read control primary inputs.
// Identified 0 write control primary inputs.
// ---------------------------------------------------------------------------
// Total number of internal lines is 351 (117 clocks, 117 sets , 117 resets, 0 reads, 0 writes).
// Total number of potentially clockable internal lines is 117 (117 clocks, 0 sets , 0 resets, 0 reads, 0 writes).
// Total number of not clockable internal lines is 234 (0 clocks, 117 sets , 117 resets, 0 reads, 0 writes).
// Total number of added primary input controls 2 (2 clocks, 0 sets , 0 resets, 0 reads, 0 writes).
// ---------------------------------------------------------------------------
// command: delete_clocks clk
// command: delete_clocks edt_clock
// command: dofile design_edt_module_edt.dofile
// command: set_edt_instances -edt_logic_top delta_sigma_modulator_edt_i
// Found edt_logic_top at path: "/delta_sigma_modulator_edt_i".
// command: set_edt_instances -decompressor delta_sigma_modulator_edt_decompressor_i
// Found decompressor at path: "/delta_sigma_modulator_edt_i/delta_sigma_modulator_edt_decompressor_i".
// command: set_edt_instances -compactor delta_sigma_modulator_edt_compactor_i
// Found compactor at path: "/delta_sigma_modulator_edt_i/delta_sigma_modulator_edt_compactor_i".
// command: add_scan_groups group1 design_edt_module_edt.testproc
// command: add_scan_chains -internal 1 group1 /delta_sigma_modulator_i/scan_in0 /delta_sigma_modulator_i/scan_out0
// command: add_scan_chains -internal 2 group1 /delta_sigma_modulator_i/scan_in1 /delta_sigma_modulator_i/scan_out1
// command: add_clocks 0 clk
// command: add_clocks 1 rst_n
// command: add_clocks 0 edt_clock
// command: add_pin_constraints test_mode C1
// command: add_pin_constraints edt_clock C0
// command: set_edt_options -channels 1 -bypass_chains 1 -initialization_cycles 12 -bypass_logic on -clocking edge -longest_chain_range 2 47 -reset_signal off -pulse_edt_before_shift_clocks off -ip_version 8 -decompressor_size 9 -injectors_per_channel 4 -scan_chains 2 -xor_taps_per_chain 3 -compactor_type xpress -lockup on -retime_chain_boundaries off -bypass_chain_change_edge on
// command: set_decompressor_connections -channel 1 -taps 1 3 8 6
// command: set_edt_pins output_channels -compactor_pipeline_stages 0
// command: set_edt_pins output_channel -change_edge_at_compactor_output trailing_edge_of_edt_clock
// command: set_decompressor_connections -chain 1 -taps 1 5 6
// command: set_decompressor_connections -chain 2 -taps 3 7 9
// command: set_bypass_chains -bypass_chain_number 1 -edt_chains 1 2
// command: set_mask_register -input_channel_mask_register_sizes 1 3
// command: set_mask_decoder_connections -mode_bit 1 3
// command: set_mask_decoder_connections -1hot_decoder 1 1 2 1 1
// command: set_mask_decoder_connections -xor_decoder 1 1 2
// command: set_mask_decoder_connections -xor_decoder 2 1 1
// command: set_attribute_value {clk edt_clock} -name is_excluded_from_isolation_constraints
// command: set_system_mode analysis
// ---------------------------------------------------------------------------
// Begin scan chain identification process, memory elements = 117.
// ---------------------------------------------------------------------------
// Reading group test procedure file design_edt_module_edt.testproc.
// Begin simulation of load_unload procedure.
// Simulation of load_unload procedure completed, CPU time=0.0 sec.
// ---------------------------------------------------------------------------
// Begin EDT Finder analyses.
// ---------------------------------------------------------------------------
// Finding EDT logic.
// Finding internal scan chains.
// EDT Finder completed, EDT blocks=1, scan chains=2, CPU time=0.00 sec.
// ---------------------------------------------------------------------------
// Chain = 1 successfully traced with scan_cells = 47.
// Chain = 2 successfully traced with scan_cells = 47.
// 1 external shadows that use shift clocking have been identified.
// 94 scan cells have been identified in 2 scan chains.
// Longest scan chain has 47 scan cells.
// Warning: 1 edge-triggered clock ports set to stable high. (D7)
// ---------------------------------------------------------------------------
// Begin EDT setup and rules checking.
// ---------------------------------------------------------------------------
// Running EDT Pattern Generation Phase.
// EDT setup and rules checking completed, CPU time=0.01 sec.
// Warning: EDT initialization cycles increase each pattern size by 26%.
// ---------------------------------------------------------------------------
// Begin scan clock rules checking.
// ---------------------------------------------------------------------------
// 3 scan clock/set/reset lines have been identified.
// All scan clocks successfully passed off-state check.
// 22 sequential cells passed clock stability checking.
// There were 1 clock rule C3 fails (clock may capture data affected by its captured data).
// Capture clock is set to clk.
// Note: Trailing edge triggered device can capture data affected by leading edge.
// ---------------------------------------------------------------------------
// 22 non-scan memory elements are identified.
// ---------------------------------------------------------------------------
// 22 non-scan memory elements are identified as INIT-X. (D5)
// ---------------------------------------------------------------------------
// 8 gates may have an observable X-state. (E5)
// command: write_core_description modulator_final.tcd -replace
// command: set_fault_type stuck
// command: create_patterns
No faults in fault list. Adding all faults...
// | ------------------------------------------------------------------------------------------------------------------ |
// | Analyzing the design |
// | |
// | Current clock restriction setting: Domain_clock (edge interaction) |
// | (optimal) |
// | |
// | Current abort limit setting: 30 |
// | Calling: set_abort_limit 300 100 |
// | ------------------------------------------------------------------------------------------------------------------ |
// | |
// | Current sequential depth: 0 |
// | Optimal sequential depth: 1 |
// | Calling: set_pattern_type -sequential 1 |
// | |
// | ------------------------------------------------------------------------------------------------------------------ |
// Error: Port 'clk' is not controlled. Every port must be controlled/constrained when generating retargetable patterns and not left for ATPG to specify. (R7-1)
// Error: There was 1 R7 violation (port is not controlled/constrained during generation of retargetable patterns).
// 'DOFile 3_modulator_edt_atpg.tcl' aborted at line 17
脚本文件如下:
set_context patterns -scan
read_verilog design_edt_module_edt_top_gate.v
read_cell_library /home/jjt/chirp_ijtag/lib/tcb013ghp.mdt
set_current_mode -type internal
report_clocks
add_input_constraints scan_enable -C1
add_input_constraints test_mode -C1
add_input_constraints rst_n -C1
analyze_control_signals -auto_fix
delete_clocks clk
delete_clocks edt_clock
dofile design_edt_module_edt.dofile
set_attribute_value {clk edt_clock} -name is_excluded_from_isolation_constraints
set_system_mode analysis
write_core_description modulator_final.tcd -replace
set_fault_type stuck
create_patterns
write_patterns modulator.retpat -patdb -replace
write_faults modulator_stuck.faults.gz -replace
write_flat_model modulator_stuck.flat_model.gz -replace
quit
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