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本帖最后由 ajianer 于 2010-1-22 21:20 编辑
6 • 2008 IEEE International Solid-State Circuits Conference 978-1-4244-2010-0/08/$25.00 ©2008 IEEE
Foreword................................................................................................................................3
Reflections................................................................................................................................5
Evening Sessions
SE1 Green Electronics: Environmental Impacts, Power, E-Waste................................................................................................12
SE2 MEMS for Frequency Synthesis and Wireless RF Communications (or Life without Quartz Crystal)..................................................14
Session 1: Plenary Session
Session Overview and Abstracts................................................................................................................................16
1.1 The 2nd Wave of Digital Consumer Revolution: Challenges and Opportunities...........................................................................18
1.2 Surface and Tangible Computing, and the “Small” Matter of People and Design.......................................................................24
Awards................................................................................................................................... ...........................30
1.3 Embedded Processing at the Heart of Life and Style..........................................................................................................32
1.4 Why Can’t A Computer Be More Like A Brain? Or What To Do With All Those Transistors?..............................................................38
Session 2: Image Sensors & Technology
Session Overview and Abstracts................................................................................................................................42
2.1 A 128×128 Single-Photon Imager with on-Chip Column-Level 10b Time-to-Digital Converter Array Capable of 97ps Resolution...............44
2.2 A 5000S/s Single-Chip Smart Eye-Tracking Sensor............................................................................................................46
2.3 A 3MPixel Multi-Aperture Image Sensor with 0.7μm Pixels in 0.11μm CMOS...........................................................................48
2.4 A 140dB-Dynamic-Range MOS Image Sensor with In-Pixel Multiple-Exposure Synthesis..............................................................50
2.5 A White-RGB CFA-Patterned CMOS Image Sensor with Wide Dynamic Range...........................................................................52
2.6 A 3.6pW/frame·pixel 1.35V PWM CMOS Imager with Dynamic Pixel Readout and no Static Bias Current............................................54
2.7 A CMOS Image Sensor Integrating Column-Parallel Cyclic ADCs with On-Chip Digital Error-Correction Circuits....................................56
2.8 A 2Mpixel 1/4-inch CMOS Image Sensor with Enhanced Pixel Architecture for Camera-Phones and PC Cameras................................58
2.9 Low-Crosstalk and Low-Dark-Current CMOS Image-Sensor Technology Using a Hole-Based Detector...............................................60
2.10 A CMOS Image Sensor with a Buried-Channel Source Follower.............................................................................................62
Session 3: Filters and Amplifiers
Session Overview and Abstracts................................................................................................................................64
3.1 A Widely-Tunable Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio............................................................66
3.2 A Gain-Boosted Discrete-Time Charge-Domain FIR LPF with Double-Complementary MOS Parametric Amplifiers...............................68
3.3 A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13μm CMOS with 186MHz GBW.............................................70
3.4 A 6th-Order 100μA 280MHz Source-Follower-Based Single-Loop Continuous-Time Filter...............................................................72
3.5 A Current-Feedback Instrumentation Amplifier with 5μV Offset for Bidirectional High-Side Current-Sensing.......................................74
3.6 A BiCMOS Operational Amplifier Achieving 0.33μV/°C Offset Drift using Room-Temperature Trimming.............................................76
3.7 130dB-DR Transimpedance Amplifier with Monotonic Logarithmic Compression and a High-Current Monitor......................................78
Session 4: Microprocessors
Session Overview and Abstracts................................................................................................................................80
4.1 A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor.........................................................82
4.2 Implementation of a Third-Generation 16-Core 32-Thread CMT SPARC® Processor.....................................................................84
4.3 Migration of Cell Broadband EngineTM from 65nm SOI to 45nm SOI.........................................................................................86
4.4 TILE64TM Processor: A 64-Core SoC with Mesh Interconnect.................................................................................................88
4.5 An 8640MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by Automatic Parallelizing Compiler..............................90
4.6 A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor.................................................................................................92
4.7 Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium® Processor.............................................................94
Session 5: High-Speed Transceivers
Session Overview and Abstracts................................................................................................................................96
5.1 An 8Gb/s Transceiver with a 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for a -36.8dB-loss Backplane.............................98
5.2 A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR..............................................................................100
5.3 A 20Gb/s Duobinary Transceiver in 90nm CMOS.............................................................................................................102
5.4 A 6Gb/s RX Equalizer Adapted Using Direct Measurement of the Equalizer Output Amplitude........................................................104
5.5 A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in 0.13μm CMOS......................................................106
5.6 A Serial Data Transmitter for Multiple 10Gb/s Communication Standards in 0.13μm CMOS..........................................................108
5.7 A T-Coil-Enhanced 8.5Gb/s High-Swing Source-Series-Terminated Transmitter in 65nm Bulk CMOS...............................................110
5.8 A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration..........112
DIGEST OF TECHNICAL PAPERS • 7
Session 6: UWB Potpourri
Session Overview and Abstracts...............................................................................................................................114
6.1 A 1.8Gpulse/s UWB Transmitter in 90nm CMOS..............................................................................................................116
6.2 A 0.18μm CMOS 802.15.4a UWB Transceiver for Communication and Localization....................................................................118
6.3 A CMOS UWB Camera with 7×7 Simultaneous Active Pixels...............................................................................................120
6.4 A Fully-Integrated 14-Band 3.1-to-10.6GHz 0.13μm SiGe BiCMOS UWB RF Transceiver.............................................................122
6.5 UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking.................................................................124
6.6 A 3-to-10GHz 14-Band CMOS Frequency Synthesizer with Spurs Reduction for MB-OFDM UWB Systems.........................................126
6.7 A 0.6-to-10GHz Receiver Front-End in 45nm CMOS..........................................................................................................128
6.8 A 90nm CMOS 60GHz Radio....................................................................................................................................130
6.9 A 60kb/s-to-10Mb/s 0.37nJ/b Adaptive-Frequency-Hopping Transceiver for Body-Area Network.....................................................132
Session 7: TD: Electronics for Life Sciences
Session Overview and Abstracts...............................................................................................................................134
7.1 Life Thermoscope: Integrated Microelectronics for Visualizing Hidden Life Rhythm...................................................................136
7.2 A 1V Micropower System-on-Chip for Vital-Sign Monitoring in Wireless Body Sensor Networks....................................................138
7.3 CMOS Mini Nuclear Magnetic-Resonance System and its Application for Biomolecular Sensing...................................................140
7.4 CMOS Imager Technologies for Biomedical Applications...................................................................................................142
7.5 A 1600-pixel Subretinal Chip with DC-free Terminals and ±2V Supply Optimized for Long Lifetime and High Stimulation Efficiency........144
7.6 A 128-Channel 6mW Wireless Neural Recording IC with On-the-Fly Spike Sorting and UWB Transmitter..........................................146
7.7 A 256×256 CMOS Microelectrode Array for Extracellular Neural Stimulation of Acute Brain Slices..................................................148
7.8 A 1.12mW Continuous Healthcare Monitor Chip Integrated on a Planar Fashionable Circuit Board..................................................150
Evening Sessions
SE3 From Silicon to Aether and Back...............................................................................................................................152
SE4 Unusual Data-Converter Techniques..........................................................................................................................154
E1 Private Equity: Fight them or Invite them......................................................................................................................156
SE5 Trusting Our Lives to Sensors..................................................................................................................................158
Session 8: Medical & Displays
Session Overview and Abstracts...............................................................................................................................160
8.1 An 8μW Heterodyning Chopper Amplifier for Direct Extraction of 2μVrms Brain Biomarkers...........................................................162
8.2 A 200μW Eight-Channel Acquisition ASIC for Ambulatory EEG Systems..................................................................................164
8.3 A Microsystem for Time-Resolved Fluorescence Analysis using CMOS Single-Photon Avalanche Diodes and Micro-LEDs.....................166
8.4 A CMOS Electro-Chemical DNA-Detection Array with On-Chip ADC.......................................................................................168
8.5 A Fingerprint Sensor with Impedance Sensing for Fraud Detection.......................................................................................170
8.6 A 10b 75ns CMOS Scanning-Display-Driver System for QVGA LCDs......................................................................................172
8.7 A Direct-Type Fast Feedback Current Driver for Medium- to Large-Size AMOLED Displays...........................................................174
8.8 A Compact Low-Power CDAC Architecture for Mobile TFT-LCD Driver ICs...............................................................................176
Session 9: mm-Wave & Phased Arrays
Session Overview and Abstracts...............................................................................................................................178
9.1 A 95GHz Receiver with Fundamental-Frequency VCO and Static Frequency Divider in 65nm Digital CMOS.......................................180
9.2 A Robust 24mW 60GHz Receiver in 90nm Standard CMOS................................................................................................182
9.3 A 52GHz Phased-Array Receiver Front-End in 90nm Digital CMOS........................................................................................184
9.4 A Scalable 6-to-18GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS.........................................................186
9.5 A Near-Field Modulation Technique Using Antenna-Reflector Switching................................................................................188
9.6 A 60GHz CMOS Receiver Using a 30GHz LO..................................................................................................................190
9.7 A 22.3dB-Voltage-Gain 6.1dB-NF 60GHz LNA in 65nm CMOS with Differential Output.................................................................192
9.8 A 2kV-ESD-Protected 18GHz LNA with 4dB NF in 0.13μm CMOS...........................................................................................194
9.9 A Broadband Distributed Amplifier with Internal Feedback Providing 660GHZ GBW in 90nm CMOS...............................................196
Session 10: Cellular Transceivers
Session Overview and Abstracts...............................................................................................................................198
10.1 A Fractional-Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE.................................200
10.2 Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX-Power Control........................202
10.3 Equalization of IM3 Products in Wideband Direct-Conversion Receivers................................................................................204
10.4 A Fully-Integrated Quad-Band GPRS/EDGE Radio in 0.13μm CMOS.......................................................................................206
10.5 A 24mm2 Quad-Band Single-Chip GSM Radio in 90nm Digital CMOS.....................................................................................208
10.6 Integration of a SiP for GSM/EDGE in CMOS Technology....................................................................................................210
10.7 A Low-Power WCDMA Transmitter with an Integrated Notch Filter........................................................................................212
10.8 A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB [email=EVM@-3dBm]EVM@-3dBm[/email] and a Choke/Coil-Less Pre-Power Amplifier..........................214
10.9 A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS..........................................216
8 • 2008 IEEE International Solid-State Circuits Conference 978-1-4244-2010-0/08/$25.00 ©2008 IEEE
Session 11: Optical Communication
Session Overview and Abstracts...............................................................................................................................218
11.1 A 2.7V 9.8Gb/s Burst-Mode TIA with Fast Automatic Gain Locking and Coarse Threshold Extraction...............................................220
11.2 A 10Gb/s Laser-Diode Driver with Active Back-Termination in 0.18μm CMOS..........................................................................222
11.3 A 20/10/5/2.5Gb/s Power-Scaling Burst-Mode CDR Using GVCO/Div2/DFF Tri-mode Cells............................................................224
11.4 A 10.3125Gb/s Burst-Mode CDR Using a ΔΣ DAC...........................................................................................................226
11.5 A 40Gb/s CDR Circuit with Adaptive Decision-Point Control Using Eye-Opening-Monitor Feedback.................................................228
11.6 A 96Gb/s-Throughput Transceiver for Short-Distance Parallel Optical Links............................................................................230
11.7 A 90nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion
Compensation of Multi-mode Optical Fibers at 10Gb/s..................................................................................................232
11.8 A 10Gb/s MLSE-based Electronic-Dispersion-Compensation IC with Fast-Power-Transient Management for WDM Add/Drop Networks......234
Session 12: High-Efficiency Data Converters
Session Overview and Abstracts...............................................................................................................................236
12.1 An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS........................................................................238
12.2 Highly-Interleaved 5b 250MS/s ADC with Redundant Channels in 65nm CMOS........................................................................240
12.3 A 150MS/s 133μW 7b ADC in 90nm Digital CMOS Using a Comparator-Based Asynchronous Binary-Search Sub-ADC..........................242
12.4 A 1.9μW 4.4fJ/conversion-step 10b 1MS/s Charge-Redistribution ADC..................................................................................244
12.5 A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator................................................................................246
12.6 A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC................................................................................248
12.7 A 1.2V 4.5mW 10b 100MS/s Pipelined ADC in 65nm CMOS................................................................................................250
12.8 A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS..........................................................................................252
Session 13: Mobile Processing
Session Overview and Abstracts...............................................................................................................................254
13.1 A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm High-К Metal-Gate CMOS............256
13.2 A 45nm 3.5G Baseband-and-Multimedia-Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques..................258
13.3 A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU................................260
13.4 A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded
Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.........................................................................262
13.5 A 58mW 1.2mm² HSDPA Turbo-Decoder ASIC in 0.13μm CMOS...........................................................................................264
13.6 An 11mm2 70mW Fully-Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12μm CMOS.................................266
Session 14: Embedded & Graphics DRAM
Session Overview and Abstracts...............................................................................................................................268
14.1 A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS.................................................................................270
14.2 A 170GB/s 16Mb Embedded DRAM with Data-Bus Charge-Recycling.....................................................................................272
14.3 A 2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process........................................................274
14.4 An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications..............................................................................276
14.5 A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques........................................278
14.6 Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface............................280
14.7 A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle-Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS........282
Session 15: TD: Trends in Signal & Power Transmission
Session Overview and Abstracts...............................................................................................................................284
15.1 A CMOS-SOI 2.45GHz Remote-Powered Sensor Tag.........................................................................................................286
15.2 A Triple-Band Passive RFID Tag...............................................................................................................................288
15.3 An Inductively Coupled 64b Organic RFID Tag operating at 13.56MHz with a Data Rate of 787b/s...................................................290
15.4 A 107pJ/b 100kb/s 0.18μm Capacitive-Coupling Transceiver for Printable Communication Sheet...................................................292
15.5 A <5mW/Gb/s/link 16×10Gb/s Bi-Directional Single-Chip CMOS Optical Transceiver for Board-Level Optical Interconnects....................294
15.6 Next-Generation Smart-Power Technologies — Challenges and Innovations Enabling Complex SoC Integration.................................296
15.7 An 11Gb/s Inductive-Coupling Link with Burst Transmission...............................................................................................298
15.8 A Capacitive Power-Management Circuit for Micropower Thermoelectric Generators with a 2.1μW Controller....................................300
15.9 A Full-Wave Rectifier for Interfacing with Multi-Phase Piezoelectric Energy Harvesters.............................................................302
Session 16: Low-Power Digital
Session Overview and Abstracts...............................................................................................................................304
16.1 iVisual: An Intelligent Visual Sensor SoC with 2790fps CMOS Image Sensor and 205GOPS/W Vision Processor..................................306
16.2 A 125GOPS 583mW Network-on-Chip-Based Parallel Processor with Bio-inspired Visual-Attention Engine.......................................308
16.3 A 360mW 105Mb/s DVB-S2-Compliant Codec based on 64800b LDPC and BCH Codes enabling Satellite-Transmission Portable Devices....310
16.4 A 512GOPS Fully-Programmable Digital Image Processor with full HD 1080p Processing Capabilities...........................................312
16.5 A 242mW 10mm2 1080p H.264/AVC High-Profile Encoder Chip............................................................................................314
16.6 A 320mV 56μW 411GOPS/Watt Ultra-Low-Voltage Motion-Estimation Accelerator in 65nm CMOS..................................................316
16.7 A 65nm Sub-Vt Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter....................................................318
DIGEST OF TECHNICAL PAPERS • 9
Session 17: Wideband Receivers
Session Overview and Abstracts...............................................................................................................................320
17.1 A Discrete-Time Mixing Receiver Architecture in 65nm CMOS with Wideband Harmonic Rejection.................................................322
17.2 A Single-Inductor Dual-Band VCO in a 0.06mm2 5.6GHz Multi-Band Front-End in 90nm Digital CMOS..............................................324
17.3 A Wideband Balun LNA I/Q-Mixer Combination in 65nm CMOS...........................................................................................326
Session 18: TD: MOS Medley
Session Overview and Abstracts...............................................................................................................................328
18.1 A 64/256-Element Thermopile Infrared-Sensor Chip with 4 Built-In Amplifiers for use in Atmospheric-Pressure Conditions...................330
18.2 Measurement of Nano-Displacement Based on In-Plane Suspended-Gate MOSFET Detection
Compatible with a Front-End CMOS Process................................................................................................................332
18.3 Ultra-Thin Chips on Foil for Flexible Electronics.............................................................................................................334
18.4 A 0.18μm CMOS Integrated Sensor for the Rapid Identification of Bacteria.............................................................................336
Session 19: PLLs & Oscillators
Session Overview and Abstracts...............................................................................................................................338
19.1 A Low-Noise Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping
Time-to-Digital Converter and Quantization Noise Cancellation.........................................................................................340
19.2 Spurious-Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL....................................................342
19.3 A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction...............................344
19.4 A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering.....................................346
19.5 A 90μW 12MHz Relaxation Oscillator with a -162dB FOM..................................................................................................348
19.6 A 0.5-to-480MHz Self-Referenced CMOS Clock Generator with 90ppm Total Frequency Error and Spread-Spectrum Capability................350
19.7 A Temperature-Compensated Digitally-Controlled Crystal Pierce Oscillator for Wireless Applications.............................................352
Session 20: WLAN/WPAN
Session Overview and Abstracts...............................................................................................................................354
20.1 A 1×2 MIMO Multi-Band CMOS Transceiver with an Integrated Front-End in 90nm CMOS for 802.11a/g/n WLAN Applications..................356
20.2 A Dual-Band CMOS MIMO Radio SoC for 802.11n Wireless LAN..........................................................................................358
20.3 A Fully-Digital 65nm CMOS Transmitter for the 2.4-to-2.7GHz WiFi/WiMAX Bands using 5.4GHz ΔΣ RF DACs....................................360
20.4 A Scalable 2.4-to-2.7GHz WiFi/WiMAX Discrete-Time Receiver in 65nm CMOS........................................................................362
20.5 A Single-Chip CMOS Radio SoC for v2.1 Bluetooth Applications..........................................................................................364
20.6 A 0.6V 32.5mW Highly-Integrated Receiver for 2.4GHz ISM-Band Applications........................................................................366
20.7 A 5.4mW 0.07mm2 2.4GHz Front-End Receiver in 90nm CMOS for IEEE 802.15.4 WPAN..............................................................368
20.8 A 2.4GHz 3.6mW 0.35mm2 Quadrature Front-End RX for ZigBee and WPAN Applications.............................................................370
20.9 A DDFS-Driven Mixing-DAC with Image and Harmonic Rejection Capabilities..........................................................................372
Session 21: SRAM
Session Overview and Abstracts...............................................................................................................................374
21.1 A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology.......376
21.2 A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management..................378
21.3 A High-Density 45nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing................................................................380
21.4 A Single-Power-Supply 0.7V 1GHz 45nm SRAM with a Asymmetrical Unit-β-Ratio Memory Cell....................................................382
21.5 A 65nm Low-Power High-Density SRAM Operable at 1.0V Under 3σ Systematic Variation
Using Separate Vth Monitoring and Body Bias for NMOS and PMOS.....................................................................................384
21.6 A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias
Scheme and Adaptive Block Redundancy...................................................................................................................386
21.7 A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS........................................388
21.8 An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices.......................................................390
Evening Sessions
SE6 Highlights of IEDM 2007........................................................................................................................................392
SE7 Trends and Challenges in Optical Communications Front-End.............................................................................................394
E2 Can Multicore Integration Justify the Increased Cost of Process Scaling?...............................................................................396
10 • 2008 IEEE International Solid-State Circuits Conference 978-1-4244-2010-0/08/$25.00 ©2008 IEEE
Session 22: Variation Compensation & Measurement
Session Overview and Abstracts...............................................................................................................................398
22.1 Razor II: In-Situ Error Detection and Correction for PVT and SER Tolerance.............................................................................400
22.2 Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery
Circuits for Dynamic-Variation Tolerance...................................................................................................................402
22.3 A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency..................................................404
22.4 A Commercial Field-Programmable Dense eFUSE-Array Memory with 99.999% Sense Yield for 45nm SOI CMOS...............................406
22.5 An All-Digital On-Chip Process-Control Monitor for Process-Variability Measurements..............................................................408
22.6 Compact In-Situ Sensors for Monitoring Negative-Bias-Temperature-Instability Effect and Oxide Degradation...................................410
22.7 A Completely-Digital On-Chip Circuit for Local-Random-Variability Measurement....................................................................412
22.8 1200μm2 Physical Random-Number Generators Based on a SiN MOSFET for Secure Smart-Card Applications....................................414
22.9 A Charge-Injection-Based Active-Decoupling Technique for Inductive-Supply-Noise Suppression..................................................416
Session 23: Non-Volatile Memory
Session Overview and Abstracts...............................................................................................................................418
23.1 A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm..............................................................420
23.2 A 4b/Cell 8Gb NROM Data-Storage Memory with Enhanced Write Performance.......................................................................422
23.3 A 45nm Self-Aligned-Contact-Process 1Gb NOR Flash with 5MB/s Program Speed...................................................................424
23.4 A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface.................................................426
23.5 A Multi-Level-Cell Bipolar-Selected Phase-Change Memory..............................................................................................428
23.6 A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology.............................................................................430
Session 24: Analog Power Techniques
Session Overview and Abstracts...............................................................................................................................432
24.1 A 1.2mW 1.6Vpp-Swing Class-AB 16ΩHeadphone Driver Capable of Handling Load Capacitance up to 22nF......................................434
24.2 A High-Performance Digital-Input Class-D Amplifier with Direct Battery Connection in a 90nm Digital CMOS Process..........................436
24.3 A 1V 16.9ppm/°C 250nA Switched-Capacitor CMOS Voltage Reference..................................................................................438
24.4 An Auto-Selectable-Frequency Pulse-Width Modulator for Buck Converters with Improved Light-Load Efficiency................................440
24.5 A 0.9V 0.35μm Adaptively-Biased CMOS LDO Regulator with Fast Transient Response..............................................................442
24.6 A 4-Output Single-Inductor DC-DC Buck Converter with Self-Boosted Switch Drivers and 1.2A Total Output Current.............................444
24.7 Load-Independent Control of Switching DC-DC Converters with Freewheeling Current Feedback...................................................446
24.8 A 10MHz-Bandwidth 2mV-Ripple PA-Supply Regulator for CDMA Transmitters.........................................................................448
Session 25: Building Blocks for High-Speed Transceivers
Session Overview and Abstracts...............................................................................................................................450
25.1 A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS.........................................................452
25.2 An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of PLL and Recirculating DLL......................................454
25.3 A 1ps-Resolution 2ns-Span 10Gb/s Data-Timing Generator with Spectrum Conversion...............................................................456
25.4 A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator...................................................................................458
25.5 A 94GHz Locking-Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS.........................................................460
25.6 A 1.8W 115Gb/s Serial Link for Fully Buffered DIMM with 2.1ns Pass-Through Latency in 90nm CMOS..........................................462
25.7 A 90nm CMOS Dual-Channel Powerline Communication AFE for Home-Plug AV with a Gb extension...............................................464
25.8 A 3.5mW W-band Frequency Divider with Wide Locking Range in 90nm CMOS......................................................................466
25.9 An 8×3.2Gb/s Parallel Receiver with Collaborative Timing Recovery.....................................................................................468
Session 26: Wireless Frequency Generation
Session Overview and Abstracts...............................................................................................................................470
26.1 A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna..................................................................................472
26.2 A 1.4mW 4.90-to-5.65GHz Class-C CMOS VCO with an Average FoM of 194.5dBc/Hz................................................................474
26.3 A 324GHz CMOS Frequency Generator Using a Linear-Superposition Technique......................................................................476
26.4 A 1V 220MHz-Tuning-Range 2.2GHz VCO Using a BAW Resonator......................................................................................478
26.5 A 56-to-65GHz Injection-Locked Frequency Tripler with Quadrature Outputs in 90nm CMOS.........................................................480
26.6 A 28GHz Low-Phase-Noise CMOS VCO Using an Amplitude-Redistribution Technique................................................................482
26.7 A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS............................................................................484
Session 27: ΔΣ Data Converters
Session Overview and Abstracts...............................................................................................................................486
27.1 A 108dB-SNR 1.1mW Oversampling DAC with a Three-Level DEM Technique..........................................................................488
27.2 A 0.7V 36μW 85dB-DR Audio ΔΣ Modulator Using a Class-C Inverter...................................................................................490
27.3 An Inverter-Based Hybrid ΔΣ Modulator......................................................................................................................492
27.4 A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR.........................................................494
27.5 A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT ΔΣ ADC for 802.11n/WiMax Receivers.........................496
27.6 A 100mW 10MHz-BW CT ΔΣ Modulator with 87dB DR and -91dBc IMD..................................................................................498
27.7 A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection.......................................................500
27.8 A CT ΔΣ ADC for Voice Coding with 92dB DR in 45nm CMOS..............................................................................................502
DIGEST OF TECHNICAL PAPERS • 11
Session 28: Non-Volatile Memory & Digital Clocking
Session Overview and Abstracts...............................................................................................................................504
28.1 A 16Gb 3b/Cell NAND Flash Memory in 56nm with 8MB/s Write Rate.....................................................................................506
28.2 An 8KB EEPROM-Emulation DataFLASH Module for Automotive MCU....................................................................................508
28.3 A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure.....................................510
28.4 Resonant Global Clock-Distribution for the Cell Broadband-EngineTM Processor........................................................................512
28.5 A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation.........................................................................514
28.6 A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS......................................516
28.7 A 9.5GHz 6ps-Skew Space-Filling-Curve Clock Distribution with 1.8V Full-Swing Standing-Wave Oscillators.....................................518
Session 29: TD: Trends in Communication Circuits & Systems
Session Overview and Abstracts...............................................................................................................................520
29.1 A 2.4GHz MEMS-Based Transceiver...........................................................................................................................522
29.2 A 2GHz 52μW Wake-Up Receiver with -72dBm Sensitivity Using Uncertain-IF Architecture...........................................................524
29.3 A Fully-Integrated UHF Receiver with Multi-Resolution Spectrum-Sensing (MRSS)
Functionality for IEEE 802.22 Cognitive-Radio Applications..............................................................................................526
29.4 Advanced Planar Bulk and Multigate CMOS technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies............................528
29.5 Digital Detection of Oxide Breakdown and Life-Time Extension in Submicron CMOS Technology....................................................530
29.6 Superconductive Single-Flux-Quantum Circuit/System Technology and 40Gb/s Switch System Demonstration...................................532
29.7 A Wireless Dual-Link System for Sensor-Network Applications............................................................................................534
29.8 A 400μW 4.7-to-6.4GHz VCO under an Above-IC inductor in 45nm CMOS................................................................................536
Session 30: Data Converter Techniques
Session Overview and Abstracts...............................................................................................................................538
30.1 An Over-60dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp with 30dB Loop Gain...............................540
30.2 A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS...................................................................................................542
30.3 A 24GS/s 6b ADC in 90nm CMOS...............................................................................................................................544
30.4 A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS................................................................546
30.5 A 90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive
Interpolation Time-to-Digital Converter with On-Chip Characterization................................................................................548
30.6 A Clockless ADC/DSP/DAC System with Activity-Dependent Power Dissipation and No Aliasing.....................................................550
30.7 A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOS..............................................................552
30.8 A 6b 0.2-to-0.9V Highly-Digital Flash ADC with Comparator Redundancy...............................................................................554
Session 31: RF & mm-Wave Power Amplifiers
Session Overview and Abstracts...............................................................................................................................556
31.1 TX and RX Front-Ends for the 60GHz Band in 90nm Standard Bulk CMOS................................................................................558
31.2 A 60GHz 1V +12.3dBm Transformer-Coupled Wideband PA in 90nm CMOS..............................................................................560
31.3 60 and 77GHz Power Amplifiers in Standard 90nm CMOS..................................................................................................562
31.4 A Single-Chip WCDMA Envelope-Reconstruction LDMOS PA with 130MHz Switched-Mode Power Supply.........................................564
31.5 A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation..........................................566
31.6 An Outphasing PA for a Software-Defined Radio Transmitter...............................................................................................568
31.7 A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier........................................................................................570
31.8 Balanced SiGe PA Module for Multi-Band and Multi-Mode Cellular-Phone Applications..............................................................572
Session 32: MEMS & Sensors
Session Overview and Abstracts...............................................................................................................................574
32.1 A CMOS Temperature-to-Digital Converter with an Inaccuracy of ±0.5°C (3σ) from -55 to 125°C.....................................................576
32.2 A 1.5μW 1V 2nd-Order ΔΣ Sensor Front-End with Signal Boosting and Offset Compensation for a Capacitive 3-Axis Micro-Accelerometer....578
32.3 A Mode-Matching ΔΣ Closed-Loop Vibratory-Gyroscope Readout Interface with a 0.004°/s/√Hz Noise Floor over a 50Hz Band................580
32.4 An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation.......................................................................................582
32.5 A Chopper-Stabilized Lateral-BJT-Input Interface in 0.6μm CMOS for Capacitive Accelerometers...................................................584
32.6 Single-Chip CMOS Analog Sensor-Conditioning ICs With Integrated Electrically-Adjustable Passive Resistors...................................586
32.7 A 100μW 64×128-Pixel Contrast-Based Asynchronous Binary Vision Sensor for Wireless Sensor Networks.......................................588
32.8 A 16×16 CMOS Proton Camera Array for Direct Extracellular Imaging of Hydrogen-Ion Activity......................................................590
Continuations of Papers.........................................................................................................................................593
Glossary...........................................................................................................................................................640
Tutorials...........................................................................................................................................................645
Short Course.....................................................................................................................................................648
Forums............................................................................................................................................................650
Student Forum.................................................................................................................................................664
Index of Authors..................................................................................................................................................666
Executive Committee............................................................................................................................................672
Program Committee.............................................................................................................................................673
Marriott Hotel Maps.............................................................................................................................................677
2008 Call for Papers.............................................................................................................................................679
Timetable.........................................................................................................................................................680
session01
Plenary Session
[ 本帖最后由 ajianer 于 2008-2-25 23:54 编辑 ] |
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发表于 2008-2-25 23:21:11
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