A9soc包缺少前仿库文件，请帮忙提供T家的这三个仿真verilog文件

Newstyle

打开文件 /a9soc/a9soc/verify/env/filelists/vlists/chip.vlist
会发现需要T家28的前仿库(stdcell和IO）

/project/libraries/foundry/TSMC/28HPCP/STD/Front_End/verilog/tcbn28hpcplusbwp7t40p140_110a/tcbn28hpcplusbwp7t40p140.v
/project/libraries/foundry/TSMC/28HPCP/IO/tphn28hpcpgv18_170b/AN61001_20180929/TSMCHOME/digital/Front_End/verilog/tphn28hpcpgv18_110a/tphn28hpcpgv18.v
-v /project/foundry/TSMC/28HPCP/IO/20190113/tphn28hpcpgv18od33_rgm2_c161122_170a/tphn28hpcpgv18od33_rgm2_c161122.v


也就是说，请那位兄弟提供一下
tcbn28hpcplusbwp7t40p140.v
tphn28hpcpgv18.v

tphn28hpcpgv18od33_rgm2_c161122.v


如果不方便，也可以提供仿真缺少的几个IOpad simulation model。

a9soc仿真命令如下：

ommand: vcs -full64 -notice -lca -kdb -ntb_opts uvm -debug_acc+all+dmptf -debug_region+cell+encrypt \
+vcs+lic+wait -vera +v2k -sverilog +notimingcheck +fsdb -debug_access+r -DTYPICAL_SDF \
-P /eda/snps/verdi/T-2022.06-SP2/share/PLI/VCS/LINUX64/novas.tab /eda/snps/verdi/T-2022.06-SP2/share/PLI/VCS/LINUX64/pli.a \
+define+UVM_OBJEC_MUST_HAVE_CONSTRUCTOR +define+UVM_NO_DEPRECATED +define+VCS_SIM \
+define+x2Gb+sg125+x8 +define+SVT_UVM_TECHNOLOGY +define+UVM_PACKER_MAX_BYTES=8000 \
+define+UVM_DISABLE_AUTO_ITEM_RECORDING +define+SVT_UART +define+SYNOPSYS_SV +define+FPGA \
-f  ./a9soc/a9soc/verify/env/filelists/vlists/chip.vlist -f ./a9soc/a9soc/verify/env/filelists/tblists/tb_rtl.lst \
-l vcs_cmp.log -o simv



如果缺少上述文件，vcs会报错，因为缺少IO文件和库文件
典型的：

"PDUW12DGZ_H_G u_PAD_PB0( .C (FROMPAD_PB0_i),  .PAD (PB0),  .I (TOPAD_PB0_o),  .OEN (TOPAD_PB0_oen),  .REN (gpiob_pur[0]));"
  Module definition of above instance is not found in the design.

Newstyle

有兄弟们支持一些吗？

Newstyle

目前缺失的module如下：
大致都是这类错误
*Error* view PDXOEDG_H_G is not defined for instance PAD_XTAL_XI
"/disk2/gitARM/a9soc/a9soc/design/top/src/gen/iopad_fpga.v", 5996:
Total        320 error(s),   97 warning(s)

Newstyle

在各位大神的鼎力帮助下，还剩下GTH，RGMII的接口PAD没有。但如果做个dummy，可以生成simv。目前遇到的问题是software没搞定。
armcc -W  -I /eda/arm/rvds41/RVCT/Data/4.1/713/include/unix/ -g --debug -c -O0 --cpu Cortex-A9.no_neon.no_vfp -I. -c -o public.o public.c
"public.c", line 65: Warning: A1608W: MOV pc,<rn> instruction used, but BX <rn> is preferred
   65 00000020  MOV pc,lr
0 Errors, 1 Warning
ARM Linker: Execution interrupted due to an illegal storage access.
make: *** [public.o] 错误 1

Newstyle

这个错误目前没查到原因。需要请教各位大神。这个是realview4.1编译的结果。如果更新为ads2024.0则 有ASM编译问题。不知道各位有什么指教的地方。

Newstyle

仿真已经搞定，多谢各位！

Newstyle

里面需要修改不少文件，以及顶层重复端口或者IO初始值赋值的问题。

Newstyle

xrun的仿真结果如下：
ronizer_dfi_alert_n.u_DWC_ddrphy_bcm21 module is using the <Double Register Synchronizer (1)> Clock Domain Crossing Method ***
DmacLiteMaster2 : Invalid HSIZE for the DMA access
DmacLiteMaster2 : Invalid HSIZE for the DMA access
0.0 ps DmacLiteMaster1 : HSize is not correct
DmacLiteMaster2 : Invalid HSIZE for the DMA access
DmacLiteMaster2 : Invalid HSIZE for the DMA access
DmacLiteMaster2 : Invalid HSIZE for the DMA access
0.0 ps DmacLiteMaster1 : HSize is not correct
DmacLiteMaster2 : Invalid HSIZE for the DMA access
DmacLiteMaster2 : Invalid HSIZE for the DMA access
DmacLiteMaster2 : Invalid HSIZE for the DMA access
0.0 ps DmacLiteMaster1 : HSize is not correct
DmacLiteMaster2 : Invalid HSIZE for the DMA access
DmacLiteMaster2 : Invalid HSIZE for the DMA access
DmacLiteMaster2 : Invalid HSIZE for the DMA access
0.0 ps DmacLiteMaster1 : HSize is not correct
DmacLiteMaster2 : Invalid HSIZE for the DMA access
DmacLiteMaster2 : Invalid HSIZE for the DMA access
DmacLiteMaster2 : Invalid HSIZE for the DMA access
DmacLiteMaster2 : Invalid HSIZE for the DMA access
DmacLiteMaster2 : Invalid HSIZE for the DMA access
Start Recording Waveform in FSDB format with cli +fsdb! If not OK, open vlog_tb_utils.v +65!
Simulation time 010us
Simulation time 020us
Simulation time 030us
Simulation time 040us
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ir_data is 1110
Simulation time 270us
jtag ID: xxxxxxxx
ir_data is 1010
Simulation time 280us
DP CTRL/STUTAS: Xxxxxxxxx
Simulation time 290us
ir_data is 1010
Simulation time 300us
DP CTRL/STUTAS write: Xxxxxxxxx
ir_data is 1010
Simulation time 310us
AP banksel write: Xxxxxxxxx
ir_data is 1011
Simulation time 320us
read AP IDR: Xxxxxxxxx
Simulation time 330us
IDR is 00000000Xxxxxxxx
ir_data is 1010
Simulation time 340us
Simulation time 350us
ir_data is 1011
Simulation time 360us
ir_data is 1010
Simulation time 370us
ir_data is 1011
Simulation time 380us
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ir_data is 1010
Simulation time 400us
ir_data is 1011
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[jtag GPIO reg]
ir_data is 1010
Simulation time 530us
ir_data is 1011
Simulation time 540us
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ir_data is 1010
Simulation time 560us
ir_data is 1011
Simulation time 570us
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ir_data is 1010
Simulation time 590us
ir_data is 1011
Simulation time 600us
Simulation time 610us
send data is 000000aa
ir_data is 1010
Simulation time 620us
ir_data is 1011
Simulation time 630us
Simulation time 640us
ir_data is 1010
Simulation time 650us
ir_data is 1011
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ir_data is 1010
Simulation time 680us
ir_data is 1011
Simulation time 690us
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Simulation time 710us
get data is xxxxxxxx
ERROR, address 00b70400 access failed, write: 000000aa, read: xxxxxxxx!!!
Simulation complete via $finish(1) at time 710201 NS + 0
./verify/env/fullchip/jtag_cpu_reg.sv:35         $finish;
xcelium> exit

Amaple

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木羽之灵

代码能有偿，分享吗