错误如下,我有 verilog 模块,我为其创建了symbol。只测试执行 AMS 模拟的模块,它有效。现在我想将其用于实际设计并用于AMS仿真。它给出以下错误。求求有没有哪位大佬知道为什么呀,崩溃
xmvlog:*E,BADBSE(我的文件路径):illegal base specification,)[2.5][2.5.1(IEEE)].
xmvlog: *E,EXPRPA (我的文件路径digital.netlist. vams, 35|23):xpecting a right parenthesis (')')[12.1(IEEE)].
xmvlog:*E,BADBSE(我的文件路径digital/netlist.vams,37|12):illegal base specification,)[2.5][2.5.1(IEEE)].
xmvlog:*E,EXPSMC(我的文件路径digital.netlist.vams,37|15): expecting a semicolon (';')[12.3.2(IEEE)].
xrun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).
Please refer to assembler.log file in netlist directory for the detailed info.*ERROR*(AMS-1247):AMS UNL netlisting has failed.
Check Simulation->Output Log->Netlister Log for errors. Correct your design and netlist again.
··.unsuccessful.
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