华大九天报错dc analysis is omitted because no dc-outputs are specified.

zzhisyyds

在华大九天运行前仿的时候报错显示：



Warning: Total 2 dangling nodes are removed.
Warning: Dangling node `net2' is removed.
Warning: Dangling node `net1' is removed.
Warning: Dangling device `vv2' is removed.
Warning: Dangling device `vv0' is removed.
Warning: Total 2 dangling devices are removed.
Warning: No dc path to ground from node `drain'.
Warning: No dc path to ground from node `gate'.
Warning: No dc path to ground from va device `xm0' inner net a1.
Warning: [/home/ZZH/simulation/ZZH/4mv2_test_schematic_ALPS/4mv2_test_schematic.netlist:21]: Only one connection to node `net0' from this line.
Warning: [/home/ZZH/simulation/ZZH/4mv2_test_schematic_ALPS/4mv2_test_schematic.netlist:19]: Only one connection to node `source' from this line.
Error:  dc analysis is omitted because no dc-outputs are specified

这是hspice网表

*test
****************************************
* Type     : hspice
* Tool     : AETHER-SE
* Date     : Mon May 13 14:28:57 2024
* User     : ZZH
* Top Design : 4mv2/test/schematic
****************************************
.hdl   "/homes/ZZH/huadajiutian/4mv2/MoS2FET/veriloga/veriloga.va"
.GLOBAL

****************************************
* Library : 4mv2
* Cell    : test
* View    : schematic
****************************************

**TopDesStart
XM0 drain gate source MoS2FET lambda = 0 sigma = 0.006
VV0 net1 0 DC 0
VV1 net0 0 DC A
VV2 net2 0 DC 3
**TopDesEnd

各位兄弟有知道为什么的吗？

chuchuang

你这网表是手写的？MM1 d g s buck model w l   你的后面几个都没有 用电路编辑器生成哈 XM0 net1 net0 net2 net1 MoS2FET W=10u L=0.5u

zzhisyyds

chuchuang 发表于 2024-5-14 10:20
你这网表是手写的？MM1 d g s buck model w l   你的后面几个都没有 用电路编辑器生成哈 XM0 net1 net0 net ...

兄弟，警告确实没有再报错了，但是他却显示我的这个mos的模型卡找不到了，这个mos是我拿veriloga生成的器件，然后改了下阈值电压生成的symbol，但是现在找不到这个模型了

                               
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