.subckt and1 A B Vdd OUT
XX1 A B Vdd N001 nand1
XX2 N001 Vdd OUT inv2
.ends and1
.subckt inv2 IN Vdd OUT
MP1 OUT IN Vdd Vdd PMOS l=0.5u w=4u
MN0 OUT IN 0 0 NMOS l=0.5u w=2u
.ends inv2
.subckt nand1 A B Vdd Out
MN1 Out A N001 N001 NMOS l=0.5u w=2u
MN2 N001 B 0 0 NMOS l=0.5u w=2u
MP1 Out A Vdd Vdd PMOS l=0.5u w=4u
MP2 Out B Vdd Vdd PMOS l=0.5u w=4u
.ends nand1