Dennis Fischette's PLL Tutorials

chaodong

Title: First Time, Every Time. Practical Advice for Phase-Locked Loop Design Success in a Modern CMOS World


Abstract:


The phase-locked loop (PLL) is an often feared and misunderstood beast. Black-box designs
from IP vendors are integrated on-chip with little understanding of the PLL's sensitivities
to process and digital noise. Inexperienced designers read the latest literature and
try to hit a "home run" with their first PLL. Ignorance of the PLL's internal workings
leads to impossible-to-meet specs and inadequate test features. The result?
Costly silicon spins, hapless debug efforts, and missed product windows.


This presentation provides a practical exploration of real-world PLL design
for clock generation and high-speed IO (e.g. PCI-Express) with emphasis on 45nm
and 65nm designs.


Topics include


- achieving a real physical feel for feedback stability
- common circuit implementations and how they can go horribly wrong
- avoiding late nights in the lab with inexpensive test and debug features
- defining, isolating, and measuring PLL jitter
- creating a tape-out checklist to ensure first-pass success
- subtle design implications of high-speed IO clocks
- real-world failures and successes

zxqwolf

look forward for more

cdting

Thanks!!!

waveguides

楼主辛苦了

joshuacp

Good.

boy1234

感谢分享

icdane

https://www.delroy.com/PLL_dir/pll.htm

彭盛輝

Good reference  data for PLL designers to study~~~
Thanks!!!

彭盛輝

Good reference  data for PLL designers to study~~~
Thanks!!!

彭盛輝

Good reference  data for PLL designers to study~~~
Thanks!!!