本帖最后由 kk2009 于 2023-8-19 11:21 编辑
A RF Transceiver Model is used to demonstrate the use of vManager to verify a complex mixed signal system. Verification is driven by a UVM test bench and includes SystemVerilog coverage, SystemVerilog assertions, and a UVM scoreboard. The system under test is modeled with Real Number Digital Mixed Signal constructs. Digital Mixed Signal representations of your complex mixed signal system can fit seamlessly into your digital verification strategy using vManager to oversee all stages of verification. This training resource, videos, quick start guide, presentations and testcase example demonstrate how to include functional verification system simulations into a vManager verification plan. The system under test for this demonstration is a low power ISM band RF Transceiver. SystemVerilog assertions and covergroups are utilized, and a UVM testbench including a scoreboard drives the system tests. Interaction with the vManager GUI and with the web interface is shown. Please look into other tabs of this knowledge resource page for videos (Part-1 and Part-2) and other associated learning resources and the example database - Quick Start Guide
- Transceiver Real Number Model Functional Specification
- Presentation Tour
- UVM Presentation - Application of UVM Verification Methodology to a Behaviorally Modeled Radio Frequency Transceiver System
- Testcase Example Database
Quick Start Guide.pdf
(203.4 KB, 下载次数: 98 )
UVM_for_RF_Transceiver.pdf
(844.49 KB, 下载次数: 98 )
vMan_SVRNM_SVA.pdf
(822.97 KB, 下载次数: 98 )
Transceiver RNM Functional Specification.pdf
(803.91 KB, 下载次数: 96 )
vMan_SVRNM_SVA.tar.gz
(160.28 KB, 下载次数: 105 )
| 
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2023-8-16 14:43:12
楼主
