PLL中TSPC2/3预分频器设计求助

佐佐木 · 发表于 2023-7-31 15:55:58

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老师要求是不能使用ETSPC结构，使用0.13um工艺做到20GHz，我目前仿真下来最多做到10G出头，已经用的是嵌入逻辑门的结构了，感觉改尺寸的效果有限，请问前辈们有没有类似的经验

LoktikVJ · 发表于 2023-7-31 18:05:06

hmm, you can’t do 20GHz in CMOS logic at 130nm, try to use CML logic with inductors to increase bandwidth.
but just to improve ETSPC:
1. use transistors with min length;
3. use min thick oxide transistors;
2. use low(super low) voltage transistors;
3. if possible, reduce amplitude of CMOS signal by decreasing power supply voltage;
4. increasing of distance between gate and source/drain if PDK allow it.
and yes, it's better to to use rf transistors for 20GHz to have more predictable result after layout.