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Design on Power-Rail ESD Clamp Circuit

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发表于 2008-1-18 23:05:32 | 显示全部楼层 |阅读模式

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Design on Power-Rail ESD Clamp Circuit for 3.3-V
I/O Interface by Using Only 1-V/2.5-V Low-Voltage
Devices in a 130-nm CMOS Process

Ming-Dou Ker, Senior Member, IEEE, Wen-Yi Chen, and Kuo-Chun Hsu, Member, IEEE

Abstract
A new power-rail electrostatic discharge (ESD) clamp
circuit for application in 3.3-V mixed-voltage input–output (I/O)
interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS
process. The devices in this power-rail ESD clamp circuit are all
1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially
designed without suffering the gate-oxide reliability issue under
3.3-V I/O interface applications. A special ESD detection circuit
realized with the low-voltage devices is designed and added in the
power-rail ESD clamp circuit to improve ESD robustness of ESD
clamp devices by substrate-triggered technique. The experimental
results verified in a 130-nm CMOS process have proven the excellent
effectiveness of this new proposed power-rail ESD clamp circuit.

Index Terms
Electrostatic discharge (ESD), ESD protection
circuit, high-voltage tolerant, power-rail ESD clamp circuit,
substrate-triggered technique.

Ker_WYChen_KCHsu_TCAS1_Oct_2006.pdf

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 楼主| 发表于 2008-1-18 23:07:20 | 显示全部楼层
CONCLUSION
A new power-rail ESD clamp circuit realized with
low-voltage devices for 1-V/3.3-V mixed-voltage I/O interface
has been successfully verified in a 130-nm 1-V/2.5-V
CMOS process. As comparing to the stand-alone STnMOS,
the turn-on speed of the STnMOS can be effectively improved
by the proposed ESD detection circuit. As well as, its HBM
(MM) ESD level can be improved from 1 kV (150 V) to 3.75
kV (250 V) for the STnMOS with a device dimension (W/L)
of m m. The ESD detection circuit has also shown
significant help on lowering the of SCR devices. This new
proposed power-rail ESD clamp circuit with the advantages
of very low leakage current, fast turn-on speed, higher ESD
robustness, and no gate-oxide reliability issue is an excellent
ESD protection solution to the mixed-voltage I/O interface with
high-voltage I/O signals
发表于 2008-1-22 13:21:45 | 显示全部楼层
很好的資料,感謝大大無私的分享。
发表于 2008-1-23 08:58:50 | 显示全部楼层
发表于 2008-1-26 19:37:31 | 显示全部楼层
感谢分享
发表于 2008-6-5 19:57:16 | 显示全部楼层
DDDDDDDDDDDDDDDDDDD
发表于 2008-6-5 20:28:20 | 显示全部楼层
qqqqqqqqqqqqqqqqq
发表于 2008-6-5 20:34:24 | 显示全部楼层
感谢分享
发表于 2008-6-5 22:25:28 | 显示全部楼层
感謝大大的分享~ 感恩! 感恩~~

日後有好文,必不吝張貼分享!
感謝大大......
发表于 2008-6-5 22:35:56 | 显示全部楼层
xiele
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