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楼主 |
发表于 2023-5-9 16:07:25
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报告是这样的：
##################################################
## ##
## C A L I B R E S Y S T E M ##
## ##
## L V S R E P O R T ##
## ##
##################################################
REPORT FILE NAME: amplifier3.lvs.report
LAYOUT NAME: /export/home/edauser/Project/Project_2016/CSMC_035/calibre/RunDirectory/LVS/amplifier3.sp ('amplifier3')
SOURCE NAME: /export/home/edauser/Project/Project_2016/CSMC_035/calibre/RunDirectory/LVS/amplifier3.src.net ('amplifier3')
RULE FILE: /export/home/edauser/Project/Project_2016/CSMC_035/calibre/RunDirectory/LVS/_cal35head.lvs_
CREATION TIME: Tue May 9 04:03:40 2023
CURRENT DIRECTORY: /export/home/edauser/Project/Project_2016/CSMC_035/calibre/RunDirectory/LVS
USER NAME: edauser
CALIBRE VERSION: v2011.2_34.26 Wed Jul 6 05:20:56 PDT 2011
OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of instances.
Error: Instances of different types or subtypes were matched.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT amplifier3 amplifier3
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME "VCC" "VDD" "vdd!"
LVS GROUND NAME "VSS" "GND" "GROUND" "gnd!"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE YES
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS FLATTEN INSIDE CELL NO
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS NO
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LAYOUT CASE NO
SOURCE CASE NO
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM 32
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Reduction
LVS REDUCE SERIES MOS NO
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCTION PRIORITY PARALLEL
LVS SHORT EQUIVALENT NODES NO
// Trace Property
TRACE PROPERTY mn(n) l l 0.06
TRACE PROPERTY mn(n) w w 0.06
TRACE PROPERTY mn(nf) l l 0
TRACE PROPERTY mn(nf) w w 0
TRACE PROPERTY mn(nd) l l 0
TRACE PROPERTY mn(nd) w w 0
TRACE PROPERTY mn(ng) l l 0
TRACE PROPERTY mn(ng) w w 0
TRACE PROPERTY mp(p) l l 0.06
TRACE PROPERTY mp(p) w w 0.06
TRACE PROPERTY mp(pd) l l 0
TRACE PROPERTY mp(pd) w w 0
TRACE PROPERTY q(pn) a a 0
TRACE PROPERTY q(p2) a a 0
TRACE PROPERTY q(p3) a a 0
TRACE PROPERTY d(dn) a a 0
TRACE PROPERTY d(dm) a a 0
TRACE PROPERTY d(dp) a a 0
TRACE PROPERTY d(dc) a a 0
TRACE PROPERTY d(dk) a a 0
TRACE PROPERTY d(da) a a 0
TRACE PROPERTY d(db) a a 0
TRACE PROPERTY c(cp) c c 1
TRACE PROPERTY r(rt) r r 0
TRACE PROPERTY r(rs) r r 0
TRACE PROPERTY c(cm) c c 0
TRACE PROPERTY r(rw) r r 0
TRACE PROPERTY r(an) r r 0
TRACE PROPERTY r(ap) r r 0
TRACE PROPERTY r(po) r r 0
TRACE PROPERTY r(pl) r r 0
TRACE PROPERTY r(ph) r r 0
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of instances (see below).
Error: Instances of different types or subtypes were matched.
LAYOUT CELL NAME: amplifier3
SOURCE CELL NAME: amplifier3
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 5 5
Nets: 14 14
Instances: 22 8 * MN (4 pins)
58 6 * MP (4 pins)
1 1 C (2 pins)
0 1 * R (2 pins)
------ ------
Total Inst: 81 16
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 5 5
Nets: 13 13
Instances: 6 6 MN (4 pins)
6 6 MP (4 pins)
1 1 C (2 pins)
0 1 * R (2 pins)
1 1 _smn2b (5 pins)
------ ------
Total Inst: 14 15
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 C56(138.715,-70.200) C(CP) CC1 C(C1)
bad component subtype
--------------------------------------------------------------------------------------------------------------
2 ** missing instance ** RR0 R(AN)
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 5 5 0 0
Nets: 13 13 0 0
Instances: 6 6 0 0 MN(N)
6 6 0 0 MP(P)
1 1 0 0 C(C1)
0 0 0 1 R(AN)
1 1 0 0 _smn2b
------- ------- --------- ---------
Total Inst: 14 14 0 1
o Statistics:
76 layout mos transistors were reduced to 10.
66 mos transistors were deleted by parallel reduction.
o Initial Correspondence Points:
Ports: VDD VSS OUT VN VP
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time: 0 sec
Total Elapsed Time: 0 sec
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