马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
ADI招聘数字验证岗,如果有想法,欢迎邮件nannan.cui@analog.com 联系,我们不卷,氛围和谐,等你来哈~
Digital VerificationEngineer Team
- The team handles verification of the products which include portable consumer, digital signal processing data-paths, embedded microprocessor systems and high-end power ICs.
- As an experienced engineer in this group, candidate will work with the latest verification methodologies on designs ranging from individual blocks to chip level and system level verification for these SoCs at application level.
Requirements
- Electronic Engineering/Computer Engineering degree with 3+ years of progressive experience in digital verification.
- Should have demonstrated experience in developing UVM-based testbench infrastructure from ground up, functional cover point development, code coverage analysis/closure and assertion development.
- Knowledge in AHB/AXI/APB protocols, familiar with verification of processor based SoC designs are desirable.
- Systemverilog, C/C++, System C, TCL/Perl/Python/shell-scripting.
- Excellent debugging and analytical skills.
- Must be a self-starter, should be able to work on assignments with minimal directions.
- Experience in Mixed-signal verification and analog modeling is a big plus.
- Experience in Power IC, DSP, signal-chains is a big plus.
- Experience in RTL design/FPGA flow is a big plus.
Responsibilities · Verification of complex designs and subsystems using themost leading-edge methodologies. · Contribute and influence the decisions on methodologiesto be adopted for the verification. · Complete verification ownership – Define test plan, testsand verification methodology for block/chip level verification. Work withdesign team in generating test-plans and closure of code and functionalcoverage. · Continuous interaction with analog co-sim and firmwareteam in enabling top level chip verification aspects. · Support post-silicon verification activities of theproducts working with design, product evaluation and applications engineeringteam. · If a senior level, need to lead a project and technicallymentor and guide junior verification engineers.
|