本帖最后由 轩辕志瑜 于 2022-12-6 14:51 编辑
lnnovus 是可以自动布局布线的软件，能自动布局布线并不代表它不会出错也不意味着你说"嘿lnnovus 给我把这代码变成版图" 他就能自己把代码变成版图， 它主要用于数字电路。virtuoso主要是编辑和检查版图多用于模拟电路的版图设计，数字电路从lnnovus流出版图也得用virtuoso检查。 虽然lnnovus可以自动布局布线但也得要版图工程师根据项目需求写tcl脚本和其他lnnovus需要的文件，一些项目需求的参数也得有经验的版图工程师才能调得来。你这最后的问题也可以说现在工厂流水线也可以实现自动化为啥还要招那么多的工人？（开机器不用工人？调整机器的生产参数不用工人？检查机器成品不用工人？给机器运输生产原料和运输机器生产的产品到仓库不用工人？维修机器不用工人？）
国外某大学的 ECE 6133 Physical Design Automation of VLSI Systems
Last Updated: 2/7/2022
Cadence Lab
Tutorial I: Cadence Innovus
innovus.pdf
(2.17 MB, 下载次数: 93 )
Tutorial II: Cadence Virtuoso
virtuoso.pdf
(1.57 MB, 下载次数: 78 )
要是看得懂就知道为啥要招版图工程师
文档内容是教你完整的跑一下Cadence Innovus 和 Cadence Virtuoso的流程
I. Introduction
CAD (Computer-Aided Design) tools are essential for IC (Integrated Circuit) design because today's ICs have tens of thousands of transistors to tens of millions of transistors so that it is impossible to design ICs without CAD tools.
A way to design ICs in short development time is to use high-level languages which have been developed for IC design. These languages are called HDL (Hardware Description Language). VHDL and Verilog are two representative HDLs.
The source files written with HDLs are then compiled and converted into netlists. This process is called synthesis. Netlists contain cells (gates) and nets. Nets are wires which connect cells. Cells come from standard cell libraries which are made by circuit designers and include complex cells such as full adder, as well as simple cells such as NAND and NOR.
Netlists are then brought into physical design level which is done on silicon to make layouts. In this step, we do floorplanning, placement and routing. Floorplanning places blocks, which are sets of cells, on silicon. Floorplanning is followed by placement which places standard cells. After placement, nets are routed automatically by routers. Power planning (routing of power/ground nets) and clock network synthesis (routing of clock nets) are also done before/after/during routing.
The final result is converted into gdsii format. This file is tested for DRC (Design Rule Checking), LVS (Layout Versus Schematic), SPICE simulation, and so on.
II. Goal of the Lab
You will do placement and routing for given netlists. The goal of this lab is to experience a few CAD tools. You will also come to see how layouts are generated from netlists, what kind of files (information) are needed for placement and routing.
III. Tools Used
Cadence Innovus will be used for floorplanning, placement and routing.
Cadence Virtuoso will be used for final layout generation.
NCSU 45nm technology will be used.
OSU Standard Cell Library will be used.
Synopsys Design Compiler was used for synthesis.
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发表于 2022-12-5 22:14:41
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