|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
Phase locked loop (PLL) has recently evolved into a more digital intensive architecture, which allows the designers to leverage Moore’s Law. It creates new opportunities in applying various digital signal processing techniques; however, it also inherits some implementation overhead compared to the conventional analog PLL. In this short talk, I will overview the latest trend of digital phase locked loop (DPLL), and several recent research outcomes, aiming to lower the overhead of DPLL implementation as well as enhance its performance beyond conventional analog PLL. Through validations from the proof-of-concept prototypes, they show some interesting directions for future DPLL evolution.
Bio:
Mike Shuo-Wei Chen received the B.S. degree from National Taiwan University, Taipei, Taiwan, in 1998 and the M.S. and Ph.D. degree from University of California, Berkeley, in 2002 and 2006, all in electrical engineering. He is an associate professor in Electrical Engineering Department at University of Southern California (USC) and holds Colleen and Roberto Padovani Early Career Chair position.
SSCS CICCedu 2019 - Digital PLL - Presented by Mike Shuo-Wei Chen.001.zip
(10 MB, 下载次数: 34 ,
售价: 2
信元资产
)
SSCS CICCedu 2019 - Digital PLL - Presented by Mike Shuo-Wei Chen.002.zip
(10 MB, 下载次数: 32 ,
售价: 2
信元资产
)
SSCS CICCedu 2019 - Digital PLL - Presented by Mike Shuo-Wei Chen.003.zip
(10 MB, 下载次数: 33 ,
售价: 2
信元资产
)
SSCS CICCedu 2019 - Digital PLL - Presented by Mike Shuo-Wei Chen.004.zip
(10 MB, 下载次数: 35 ,
售价: 2
信元资产
)
SSCS CICCedu 2019 - Digital PLL - Presented by Mike Shuo-Wei Chen.005.zip
(7.05 MB, 下载次数: 31 ,
售价: 2
信元资产
)
|
|
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2022-7-10 10:11:59
