S家ahb_vip ahb_slave_agent.monitor太消耗时间

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使用S家的ahb_vip中ahb_slave_agent的monitor去监测 interface数据传输，slave ready信号为1，一直在打印如下log信息。尽管使用UVM_NONE看不到这些log，但是整个仿真过程中该部分还是占用很多时间很多内存，很卡很慢，有没有哪些设置可以优化掉这种冗余呢？
谢谢大佬！！

ahb_slave_agt [sample_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] End of is_passive mode Block
ahb_slave_agt [sample_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] Waiting for sampled_current_hready event to be triggered
ahb_slave_agt [sample_passive_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] Updated current_hready value to 'b1, Triggering sampled_current_hready event
ahb_slave_agt [sample_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] sampled_current_hready event got triggered
ahb_slave_agt [sample_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] current_hready is detected as HIGH
ahb_slave_agt [sample_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0]          Detected current_hready as 'd1 for num_slaves 'd1
ahb_slave_agt [sample_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0]          Detected is_hmaster_valid = 'd1, current_hready_in = 'd1, observed_hmaster = 'd1
ahb_slave_agt [sample_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0]          active_xact created  AHB transaction {PORT_ID('d0) OBJECT_NUM('d-1) LOCK('b0) XACT_TYPE(IDLE_XACT) ADDR('h0) BURST_TYPE(SINGLE) BURST_LENGTH('d1) BURST_SIZE(BURST_SIZE_8BIT) STATUS(INITIAL) CURR_DATA_BEAT_NUM('d0)}
ahb_slave_agt [sample_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] passive_mode is detected as 1 for active_xact -  AHB transaction {PORT_ID('d0) OBJECT_NUM('d-1) LOCK('b0) XACT_TYPE(IDLE_XACT) ADDR('h0) BURST_TYPE(SINGLE) BURST_LENGTH('d1) BURST_SIZE(BURST_SIZE_8BIT) STATUS(INITIAL) CURR_DATA_BEAT_NUM('d0)}
ahb_slave_agt [sample_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] wait_for_passive_common is already 0
ahb_slave_agt [sample_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] Triggering new_active_xact event
ahb_slave_agt [sample_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] Setting wait_for_passive_common to 1
ahb_slave_agt [sample_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] Inside else block for write_data_to_mem for active_xact -  AHB transaction {PORT_ID('d0) OBJECT_NUM('d-1) LOCK('b0) XACT_TYPE(IDLE_XACT) ADDR('h0) BURST_TYPE(SINGLE) BURST_LENGTH('d1) BURST_SIZE(BURST_SIZE_8BIT) STATUS(INITIAL) CURR_DATA_BEAT_NUM('d0)}
ahb_slave_agt [sample_common_phase_signals] Sampled the Address Phase of beat 'd0 of a IDLE_XACT transaction
ahb_slave_agt [sample_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] address_phase_active is already 0
ahb_slave_agt [sample_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] Inside passive_mode Block
ahb_slave_agt [sample_passive_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] Detected new_active_xact event
ahb_slave_agt [sample_passive_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] Updated current_hready value to 'b1, Triggering sampled_current_hready event
ahb_slave_agt [sample_passive_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] observed_htrans = 'd0, observed_hresp = 'd0, observed_hready = 'b1, previous_hready = 'b1
ahb_slave_agt [sample_passive_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] Inside else-block observed_hready = 'd1, active_tracking_xact = 'd0
ahb_slave_agt [sample_passive_common_phase_signals] AHB_SYSTEM['d0] SLAVE['d0] Waiting for address_phase_active to become HIGH

anpengfei

去XXX_configuration文件中找找有没有什么en_XXX控制检查的，配置关掉
我只知道i2c的agent config中有enable_check，ahb的没看过……
或者看vip文档有没有相关的宏设置

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anpengfei 发表于 2022-7-1 13:47
去XXX_configuration文件中找找有没有什么en_XXX控制检查的，配置关掉
我只知道i2c的agent config中有enabl ...

好的，谢谢~~  我还没找到，再继续找找试试。

fengzhiyong123

跟你设置UVM_NONE类似，把它的ACTION改掉，设置为UVM_NO_ACITON

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fengzhiyong123 发表于 2022-7-7 11:07
跟你设置UVM_NONE类似，把它的ACTION改掉，设置为UVM_NO_ACITON

在compile option加上这个选项么，没操作过修改某个组件的ACTION。请赐教，谢谢！

fengzhiyong123

枫舞 发表于 2022-7-9 10:32
在compile option加上这个选项么，没操作过修改某个组件的ACTION。请赐教，谢谢！
...

这种uvm控制类型的命令一般是sim opt，你在仿真命令里面直接加上+uvm_set_action=“*，sample_common_phase_signals，UVM_INFO,UVM_NO_ACTION”再跑，大概率会解决你的问题，你也可以加在你的环境里面，直接调用组件的set_report_id_action函数。

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fengzhiyong123 发表于 2022-7-10 11:06
这种uvm控制类型的命令一般是sim opt，你在仿真命令里面直接加上+uvm_set_action=“*，sample_common_pha ...

非常感谢！！