tsmc 40nm design rule 求助

chmod

各位大佬，小白最近在看40nm design rule，看不懂 gate到底是到哪里的距离的规则，还请大神们帮忙解答,OD2指的是什么，还有(NW OR NT_N、((NW NOT OD2) NOT NT_N，谢谢！

刘海胖

OD2 refers to any thick oxide device, for example, OD2 = OD_18, OD_25.
TSMC uses NW and OD2 (OD_18, OD_25) to generate NW1V, PW1V, NW2V, and PW2V masks by logical
operations. Designers can draw NW only.
gate到well edge的距离

刘海胖

OD2 refers to any thick oxide device, for example, OD2 = OD_18, OD_25.
TSMC uses NW and OD2 (OD_18, OD_25) to generate NW1V, PW1V, NW2V, and PW2V masks by logical
operations. Designers can draw NW only.
gate到well edge的距离 rule里有图

tancheng

OD2 refers to any thick oxide device,for examole,OD2=OD_18,OD_25

chenyongfus

OD 是oxide diffusion, 就是有源区, 或者单晶硅做device 的区域. OD2 就是厚的oxide 有源区,用于做IO的管子, 工作电压比较高的. 后面的and /OR 之类的是逻辑运算, 就是布尔运算. 说这么多能不能发我一份40nm 的design rule, 万分感谢

昌谷

你好，能不能求一份t40的design rule呀

Tsengsink

同求一份design rule

a0201233

请问下design rule在哪个位置，找不到呀。。。

Aaaloneforce

求问您发的这份规则文件的名称是什么?只需要文件名就可以，非常感谢！