Layout designers receive immediate feedback on how a layout feature or change will impact design requirements - as they draw the layout.
Layout designers can discover electromigration issues as they're drawing the layout, and avoid problems immediately instead of waiting for a post-layout extraction.
Circuit designers can run "partial layout resimulation" to ensure that interconnect parasitics are not harming circuit performance.
Circuit designers can set electrical constraints (like matched resistance or capacitance) and pass these along to layout designers, who will receive instant feedback on whether the constraints are being met.