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[招聘] 模拟设计-上海-高通

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发表于 2021-12-1 16:12:33 | 显示全部楼层 |阅读模式

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JOBDESCRIPTION
Analog
GENERALSUMMARY:
We areseeking for Senior Analog Integrated Circuit Designers with excellent designskills who will be contributing in a team environment in the development of high-speedmixed-signal IPs in advanced CMOS processes. You will use your skills as anIntegrated Circuit designer while applying them to a vast array of processtechnologies, system applications, and new technology development. Tasks willinclude the development of block level definitions and requirements, detailedcircuit design and schematic creation, circuit simulation, manual layout,physical verification (Layout vs. Schematic and Design Rule Checking), behaviormodelling using Verilog-A or Verilog-AMS, and full chip verification in avariety of silicon process technologies.
PRINCIPALDUTIES AND RESPONSIBILITIES:
-Design automatic skills in IC custom design tools (e.g. Cadence or Mentor) for
schematiccapture, circuit simulation, full custom layout; mixed-signal circuit design;
-Physical verification skills;
-Behavior modelling skills;
-Using Verilog-A or Verilog-AMS, and full-chip functional/performanceverification
methods.
REQUIREDCOMPETENCIES:
- Tape out experience of following area: highspeed and high-resolution ADC/DAC/VGA (variable gain amplifier), high speedSERDES, high-performance VCO/PLL, LDO, etc.
- Familiarity with sub-threshold designs,familiar with 55nm/28nm/14nm CMOS process;
- Excellent understanding of device physics
- Experience performing chip level integration
- Experience in electronics test lab
-Self-motivated with good analytical and problem-solving skills. Excellent communicationand teamwork skills.
MINIMUMQUALIFICATIONS:
Advanceddegree -either MS or PhD in Electrical Engineering with proven record in
analogand mixed signal design experience.
PREFERREDQUALIFICATIONS:
-2+ years with a technical MS on analog circuit design, simulation, layoutguidance,
chiptests;
-1+ years with a technical PhD onanalog circuit design, simulation, layout guidance,
chip tests;
有兴趣的加我微信:zp1324403561(备注一下)
发表于 2022-1-4 10:59:57 | 显示全部楼层
本帖最后由 plmqa 于 2022-1-13 18:22 编辑

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