大V企业最近招聘岗位，速戳！！！（上）

蒋璧闺

联系方式：Tel：13310878819       Wechat：ivy13310878819

(Sr) ASIC Implementation Engineer /ASIC                 地点：上/北/武
职位介绍
Job Description
1. Responsible for Front-End chip implementation work from RTL2Netlist, including SOC/IP level Synthesis/STA/Formality check/Lint/CDC/Quality check.
2. Responsible for ASIC design methodology and flow development & optimization, interfacing with EDA vendors on technology.
3. Support Lint/CDC check, SDC/UPF writing.
4. Deliver constraints and closely co-work timing & power closure with P&R.

Job Requirement
1. Hand on experience of Synthesis/Formality/STA/LEC/SDC/UPF/Netlist quality check.
2. Familiar with front-end EDA tools and flows (DCG, PT, Conformal, Formality, Spyglass, GCA)
3. Familiar with unix/linux and scripts (tcl, perl, makefile etc.)
4. Experience in highspeed interface IP, high performance Core is a plus.
5. Experience in dft or physical design is a plus.
6. A high-level of self-motivation and a proactive approach to solving problems.



Display Software Engineer（显示多媒体软件）         地点：上/北/武
负责车载平台多操作系统的Display开发和调试
职位要求:
1. 具有2年以上手机或嵌入式系统底层软件开发调试经验.
2. 熟练掌握C/C++/JAVA编程及系统调试方法.
3. 具有Linux, Android下的驱动和系统开发调试经验.
4. 具有Wayland, Weston, Surface Flinger, DRM和KMS等编程和调试经验.
5. 熟悉MIPI, DSI, HDMI, DP等display相关接口及编程调试方法.
6. 熟悉ARM架构和编程，如ARMv8, Cortex A或Cortex M等.
7. 有高通、三星、瑞萨、MTK等芯片的车载平台开发经验优先.
8. 有Screen Sharing、虚拟化开发经验者优先.
9. 良好的学习沟通能力和问题分析解决能力，有责任心.


Video Software Engineer视频多媒体软件工          地点：上/北/武
职位要求:
1. 具有2年以上手机或嵌入式系统底层软件开发调试经验.
2. 熟练掌握C/C++/JAVA编程及系统调试方法.
3. 具有Linux, Android下的驱动和系统开发调试经验.
4. 具有V4L2, OMX, gstreamer, ffmpeg等编程和调试经验.
5. 熟悉H265/264/263, MPEG4, VP9/VP8, JPEG, AAC等视音频编解码技术.
6. 熟悉ARM架构和编程，如ARMv8, Cortex A或Cortex M等.
7. 有高通、三星、瑞萨、MTK等芯片的车载平台开发经验优先.
9. 良好的学习沟通能力和问题分析解决能力，有责任心.


:call:Camera Software Engineer(摄像头图像处理软件开发工程师)    :handshake地点：上/武
职位介绍
工作职责:
负责车载平台的Camera开发和调试

职位要求:
1. 具有2年以上手机或嵌入式系统底层软件开发调试经验.
2. 熟练掌握C/C++/JAVA编程及系统调试方法.
3. 具有Linux, Android, RTOS下的驱动和系统开发调试经验.
4. 具有Camera Driver, Image Sensor, ISP, 3A, IQ Tuning等编程和调试经验.
5. 熟悉MIPI, CSI, I2C等camera相关接口及编程调试方法.
6. 熟悉ARM架构和编程，如ARMv8, Cortex A或Cortex M等.
7. 有高通、三星、瑞萨、MTK等芯片的车载平台开发经验优先.
8. 有360环视、倒车开发经验者优先.
9. 良好的学习沟通能力和问题分析解决能力，有责任心.


:call:Graphic Software Engineer (Graphic软件开发 ）      :handshake地点：上/北/武
工作职责:
负责车载平台的图像渲染等graphic开发和调试

职位要求:
1. 具有2年以上手机或嵌入式系统底层软件开发调试经验.
2. 熟练掌握C/C++/JAVA编程及系统调试方法.
3. 具有Linux, Android下的驱动和系统开发调试经验.
4. 具有OpenGL ES, Vulkan, OpenCL等编程和调试经验.
5. 熟悉主流GPU架构和开发，如ARM Mali GPU, IMG GPU系列等.
6. 熟悉ARM架构和编程，如ARMv8, Cortex A或Cortex M等.
7. 有高通、三星、瑞萨、MTK等芯片的车载平台开发经验优先.
8. 有Screen Sharing、虚拟化开发经验者优先.
9. 良好的学习沟通能力和问题分析解决能力，有责任心.


:call:Linux内核驱动和BSP软件研发工程师         :handshake地点：上/武
职位介绍
Position Description:
The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the software development of Linux kernel driver and user space reference application for the ARM based processor targeting the market of the automotive SoC solution. The candidate is required to design and work out the solution from the Linux kernel device driver, SDK and the reference application.
The engineer will be working in the SiEngine R&D SW team.


Main Responsibility:
- Develop the bootloader, Linux kernel driver and test application for the SiEngine automotive SoC.
- Develop the software to enable and validate the driver.
- Build the automation validation framework (SLT) to validate/test the SoC and Linux.
- Develop the board support package and the reference application.


Required Skills:
- 5+ years of software development in automotive, embedded system or mobile.
- At least 2-years of experience in writing low-level software that interacts directly with hardware.
- Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection)
- Good experience in Linux driver development is a must.
- Good experience in using/customizing the opensource software.
- Familiar with bootloader such as ARM trusted firmware, u-boot etc.
- Experience in open source software such as buildroot, yacto, busybox, etc.
- Experience in LSIO driver such as UART/I2C/SPI/GPIO/PWM/SD/MMC is preferred.
- Experience in Linux kernel memory management, power management (DVFS, PSCI, STR) is a plus.
- Experience in HSIO driver such as PCIE/USB2/USB3/ETH/V2L4(CSI)/UFS/DRM(DSI, DP) is a big plus.
- Familiar with Git/Gerrit source code management tool.
- Familiar with scripts such as bash, python, etc.
- Excellent communication skills, good teamwork adaptability, self-motivated.


Education Requirement:
- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.



:call:SoC Validation & Driver Development Engineer 芯片验证和驱动研发工程师          :handshake地点：上/武
职位介绍
Position Description:
The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the board enablement and SoC validation work for the ARM based processor targeting the market of the automotive SoC solution. The candidate is required to be working closely with SoC design/verification, platform design and product team and work out the solution from the bare-metal, device driver to automation framework to validate our SoC.
The engineer will be working in the SiEngine R&D SW team.

Main Responsibility:
- Develop the bare metal driver to bringup and validate the SiEngine automotive SoC.
- Develop the software to enable and validate the development boards.
- Build the automation validation framework (SLT) to validate/test the SoC.
- Develop the tools for the SoC and board manufacture.
- Evaluate the power/current/frequency of SoC with the different corner(skew) chips

Required Skills:
- 5+ years of software development in automotive, embedded system or mobile.
- At least 2-years of experience in writing low-level software that interacts directly with hardware.
- Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection)
- Experience in driver development or experience in Linux driver development is a plus.
- Familiar with bootloader, Linux and any RTOS
- Familiar with board design and schematic
- Good experience in using high-speed oscilloscope, logic analyzer or other protocol analyzer.
- Experience in LSIO such as UART/I2C/SPI/GPIO/PWM/SD/MMC is preferred.
- Experience in VCS/Palladium Z1/X1/Zebu/FPGA/Trace32/System Verilog/UVM is a plus.
- Experience in HSIO such as DDR/PCIE/USB/ETH/MIPI (CSI, DSI)/UFS/DP is a big plus.
- Familiar with Git/Gerrit source code management tool.
- Familiar with scripts such as bash, python, etc.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:
- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.



:call:Physical Design Engineer/芯片后端设计工程师         :handshake地点：上/北/武
职位介绍
Job Description
Work with Front-End design team and physical design team for super large-scale SoC chip physical implementation from RTL to GDS. Focus on physical design of deep sub-micron ultra large chip including block and chip level synthesis, floorplan, place and route, timing closure, physical verification, EM/IR signoff checks etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team.

Job Requirement
1. Hands on experience in super large-scale SoC chip physical design, especially experience in 7nm FinFet technology and high-speed design implementation.
2. Solid knowledge and rich experience on synthesis, floorplan, place, CTS and routing, static timing analysis, EM/IR-drop and physical verification.
3. Project experience on hierarchical flow such as top-level partition, timing budgeting, pin assignment and Power Network Planning etc
4. Expertise with Synopsys/Cadence/Mentor EDA tools
5. Familiar with Unix/Linux environment and good at scripts
6. A high-level of self-motivation and a proactive approach to solving problems.
7. Good communication skills, strong interpersonal skills and the flexibility
8. Dedicated, hardworking, and good team player



:callSr) ASIC Implementation Engineer /ASIC实现工程师      :handshake地点：上/北/武

职位介绍
Job Description
1. Responsible for Front-End chip implementation work from RTL2Netlist, including SOC/IP level Synthesis/STA/Formality check/Lint/CDC/Quality check.
2. Responsible for ASIC design methodology and flow development & optimization, interfacing with EDA vendors on technology.
3. Support Lint/CDC check, SDC/UPF writing.
4. Deliver constraints and closely co-work timing & power closure with P&R.

Job Requirement
1. Hand on experience of Synthesis/Formality/STA/LEC/SDC/UPF/Netlist quality check.
2. Familiar with front-end EDA tools and flows (DCG, PT, Conformal, Formality, Spyglass, GCA)
3. Familiar with unix/linux and scripts (tcl, perl, makefile etc.)
4. Experience in highspeed interface IP, high performance Core is a plus.
5. Experience in dft or physical design is a plus.
6. A high-level of self-motivation and a proactive approach to solving problems.

蒋璧闺

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