IEEE JOURNAL OF SOLID STATE CIRCUITS 06年一月刊，值得一读

netking

great Post

sanhusanhu

搜了一把，不知道是不是这个目录的内容

  Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference

  
  Monolithic above-IC resonator technology for integrated architectures in mobile and wireless communication


  A 60-GHz CMOS receiver front-end


  A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package


  A 950-MHz rectifier circuit for sensor network tags with 10-m distance


  A VLSI analog computer/digital computer accelerator


  A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling


  The microarchitecture of the synergistic processor for a cell processor


  An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications


  XiSystem: a XiRisc-based SoC with reconfigurable IO module


  A reprogrammable EDGE baseband and multimedia handset SoC with 6-mbit embedded DRAM


  Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM


  A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications


  Enhanced write performance of a 64-mb phase-change random access memory


  A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter


  Design of a 128-mb SOI DRAM using the floating body cell (FBC)


  A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply


  A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme


  A 146-mm2 8-gb multi-level NAND flash memory with 70-nm CMOS technology


  PVT-aware leakage reduction for on-die caches with improved read stability


  Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor


  The implementation of a 2-core, multi-threaded itanium family processor


  Implementation of a fourth-generation 1.8-GHz dual-core SPARC V9 microprocessor


  A 90-nm variable frequency clock system for a power-managed itanium architecture processor

air7619

thank you
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bonwong

Good post

raydcj

好东西，谢谢楼主分享！！

weihang08

thanks for sharing