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发表于 2021-4-19 09:34:25
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【数字电路芯片验证工程师】
Job description:
1.Work on AI machine learning project verification using Systemverilog, UVM or C++.
2.Coworking with architects and design engineers on the function/performance test plan.
3.Responsible for test cases development and debug.
4.Implement directed and random testcase in UVM/SV/C++, as well as checkers and assertions.
5.Doing coverage analysis and bug cleanup in regression.
Minimum Requirements:
1.MS with 2+years or BS with 3+ years experience in asic/SoC design verification.
2.Experience in any PCIE/DDR/Video/arm/dsp/MCU verification is a big plus.
3. Knowledge of complex SoC DV flow from plan to coverage.
4.Strong problem solving and communication skills, team player.
5.Familiar with scripting languages like Perl, Makefile is a plus. |
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