VLSI Test Principles And Architecture

NetPal

一本非常有助于DFT工程师系统学习的参考书 《VLSI Test Principles And Architecture》,目录如下：

1 Introduction 1
Yinghua Min and Charles Stroud
1.1 Importance of Testing ........................... 1
1.2 Testing During the VLSI Lifecycle .................... 2
1.2.1 VLSI Development Process .................... 3
1.2.1.1 Design Verification .................. 4
1.2.1.2 Yield and Reject Rate ................. 5
1.2.2 Electronic System Manufacturing Process ........... 6
1.2.3 System-Level Operation ..................... 6
1.3 Challenges in VLSI Testing ........................ 8
1.3.1 Test Generation .......................... 9
1.3.2 Fault Models ............................ 11
1.3.2.1 Stuck-At Faults .................... 12
1.3.2.2 Transistor Faults ................... 15
1.3.2.3 Open and Short Faults ................ 16
1.3.2.4 Delay Faults and Crosstalk .............. 19
1.3.2.5 Pattern Sensitivity and Coupling Faults ...... 20
1.3.2.6 Analog Fault Models ................. 21
1.4 Levels of Abstraction in VLSI Testing .................. 22
1.4.1 Register-Transfer Level and Behavioral Level ......... 22
1.4.2 Gate Level ............................. 23
1.4.3 Switch Level ............................ 24
1.4.4 Physical Level ........................... 24

1.5 Historical Review of VLSI Test Technology ............... 25
1.5.1 Automatic Test Equipment .................... 25
1.5.2 Automatic Test Pattern Generation ............... 27
1.5.3 Fault Simulation .......................... 28
1.5.4 Digital Circuit Testing ...................... 28
1.5.5 Analog and Mixed-Signal Circuit Testing ........... 29
1.5.6 Design for Testability ....................... 29
1.5.7 Board Testing ........................... 31
1.5.8 Boundary Scan Testing ...................... 32
1.6 Concluding Remarks ............................ 33
1.7 Exercises ................................... 33
Acknowledgments .................................. 34
References ...................................... 34

2 Design for Testability 37
Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez
2.1 Introduction ................................. 37
2.2 Testability Analysis ............................. 40
2.2.1 SCOAP Testability Analysis ................... 41
2.2.1.1 Combinational Controllability and
Observability Calculation ............... 41
2.2.1.2 Sequential Controllability and
Observability Calculation ............... 43
2.2.2 Probability-Based Testability Analysis ............. 45
2.2.3 Simulation-Based Testability Analysis ............. 47
2.2.4 RTL Testability Analysis ..................... 48
2.3 Design for Testability Basics ........................ 50
2.3.1 Ad Hoc Approach ......................... 51
2.3.1.1 Test Point Insertion .................. 51
2.3.2 Structured Approach ....................... 53
2.4 Scan Cell Designs .............................. 55
2.4.1 Muxed-D Scan Cell ........................ 55
2.4.2 Clocked-Scan Cell ......................... 56
2.4.3 LSSD Scan Cell .......................... 57
2.5 Scan Architectures ............................. 59
2.5.1 Full-Scan Design .......................... 59
2.5.1.1 Muxed-D Full-Scan Design .............. 59
2.5.1.2 Clocked Full-Scan Design .............. 62
2.5.1.3 LSSD Full-Scan Design ................ 62
2.5.2 Partial-Scan Design ........................ 64
2.5.3 Random-Access Scan Design .................. 67
2.6 Scan Design Rules .............................. 70
2.6.1 Tristate Buses ........................... 71
2.6.2 Bidirectional I/O Ports ...................... 71
2.6.3 Gated Clocks ............................ 71
2.6.4 Derived Clocks ........................... 74
2.6.5 Combinational Feedback Loops ................. 74
2.6.6 Asynchronous Set/Reset Signals ................. 75
2.7 Scan Design Flow .............................. 76
2.7.1 Scan Design Rule Checking and Repair ............ 77
2.7.2 Scan Synthesis ........................... 78
2.7.2.1 Scan Configuration .................. 79
2.7.2.2 Scan Replacement ................... 82
2.7.2.3 Scan Reordering .................... 82
2.7.2.4 Scan Stitching ..................... 83
2.7.3 Scan Extraction .......................... 83
2.7.4 Scan Verification ......................... 84
2.7.4.1 Verifying the Scan Shift Operation ......... 85
2.7.4.2 Verifying the Scan Capture Operation ....... 86
2.7.5 Scan Design Costs ......................... 86
2.8 Special-Purpose Scan Designs ....................... 87
2.8.1 Enhanced Scan .......................... 87
2.8.2 Snapshot Scan ........................... 88
2.8.3 Error-Resilient Scan ....................... 90
2.9 RTL Design for Testability ......................... 92
2.9.1 RTL Scan Design Rule Checking and Repair ......... 93
2.9.2 RTL Scan Synthesis ........................ 94
2.9.3 RTL Scan Extraction and Scan Verification .......... 95
2.10 Concluding Remarks ............................ 95
2.11 Exercises ................................... 96
Acknowledgments .................................. 99
References ...................................... 99


3 Logic and Fault Simulation 105
Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker
3.1 Introduction ................................. 106
3.1.1 Logic Simulation for Design Verification ........... 106
3.1.2 Fault Simulation for Test and Diagnosis ............ 107
3.2 Simulation Models ............................. 108
3.2.1 Gate-Level Network ........................ 109
3.2.1.1 Sequential Circuits .................. 109
3.2.2 Logic Symbols ........................... 110
3.2.2.1 Unknown State u ................... 111
3.2.2.2 High-Impedance State Z ............... 113
3.2.2.3 Intermediate Logic States .............. 114
3.2.3 Logic Element Evaluation .................... 114
3.2.3.1 Truth Tables ...................... 115
3.2.3.2 Input Scanning .................... 115
3.2.3.3 Input Counting ..................... 116
3.2.3.4 Parallel Gate Evaluation ............... 116
3.2.4 Timing Models ........................... 118
3.2.4.1 Transport Delay .................... 118
3.2.4.2 Inertial Delay ...................... 119
3.2.4.3 Wire Delay ....................... 119
3.2.4.4 Functional Element Delay Model .......... 120
3.3 Logic Simulation .............................. 121
3.3.1 Compiled-Code Simulation ................... 121
3.3.1.1 Logic Optimization .................. 121
3.3.1.2 Logic Levelization ................... 123
3.3.1.3 Code Generation .................... 124
3.3.2 Event-Driven Simulation ..................... 125
3.3.2.1 Nominal-Delay Event-Driven Simulation ..... 126
3.3.3 Compiled-Code Versus Event-Driven Simulation ....... 129
3.3.4 Hazards ............................... 130
3.3.4.1 Static Hazard Detection ............... 131
3.3.4.2 Dynamic Hazard Detection ............. 132
3.4 Fault Simulation .............................. 132
3.4.1 Serial Fault Simulation ...................... 133
3.4.2 Parallel Fault Simulation ..................... 135
3.4.2.1 Parallel Fault Simulation ............... 135
3.4.2.2 Parallel-Pattern Fault Simulation .......... 137
3.4.3 Deductive Fault Simulation ................... 139
3.4.4 Concurrent Fault Simulation .................. 143
3.4.5 Differential Fault Simulation .................. 146
3.4.6 Fault Detection .......................... 148
3.4.7 Comparison of Fault Simulation Techniques ......... 149
3.4.8 Alternatives to Fault Simulation ................. 151
3.4.8.1 Toggle Coverage .................... 151
3.4.8.2 Fault Sampling .................... 151
3.4.8.3 Critical Path Tracing ................. 152
3.4.8.4 Statistical Fault Analysis ............... 153
3.5 Concluding Remarks ............................ 154
3.6 Exercises ................................... 155
References ...................................... 158


4 Test Generation 161
Michael S. Hsiao
4.1 Introduction ................................. 161
4.2 Random Test Generation .......................... 163
4.2.1 Exhaustive Testing ........................ 166
4.3 Theoretical Background: Boolean Difference .............. 166
4.3.1 Untestable Faults ......................... 168
Contents xi
4.4 Designing a Stuck-At ATPG for Combinational Circuits ........ 169
4.4.1 A Naive ATPG Algorithm ..................... 169
4.4.1.1 Backtracking ...................... 172
4.4.2 A Basic ATPG Algorithm ..................... 173
4.4.3 D Algorithm ............................ 177
4.4.4 PODEM ............................... 182
4.4.5 FAN ................................. 186
4.4.6 Static Logic Implications ..................... 187
4.4.7 Dynamic Logic Implications ................... 191
4.5 Designing a Sequential ATPG ....................... 194
4.5.1 Time Frame Expansion ...................... 194
4.5.2 5-Valued Algebra Is Insufficient ................. 196
4.5.3 Gated Clocks and Multiple Clocks ............... 197
4.6 Untestable Fault Identification ...................... 200
4.6.1 Multiple-Line Conflict Analysis ................. 203
4.7 Designing a Simulation-Based ATPG ................... 207
4.7.1 Overview .............................. 208
4.7.2 Genetic-Algorithm-Based ATPG ................. 208
4.7.2.1 Issues Concerning the GA Population ....... 212
4.7.2.2 Issues Concerning GA Parameters ......... 213
4.7.2.3 Issues Concerning the Fitness Function ...... 213
4.7.2.4 CASE Studies ..................... 215
4.8 Advanced Simulation-Based ATPG .................... 218
4.8.1 Seeding the GA with Helpful Sequences ............ 218
4.8.2 Logic-Simulation-Based ATPG ................. 222
4.8.3 Spectrum-Based ATPG ...................... 225
4.9 Hybrid Deterministic and Simulation-Based ATPG .......... 226
4.9.1 ALT-TEST Hybrid ......................... 228
4.10 ATPG for Non-Stuck-At Faults ...................... 231
4.10.1 Designing an ATPG That Captures Delay Defects ....... 231
4.10.1.1 Classification of Path-Delay Faults ......... 233
4.10.1.2 ATPG for Path-Delay Faults ............. 236
4.10.2 ATPG for Transition Faults ................... 238
4.10.3 Transition ATPG Using Stuck-At ATPG ............ 240
4.10.4 Transition ATPG Using Stuck-At Vectors ........... 240
4.10.4.1 Transition Test Chains via Weighted
Transition Graph ................... 241
4.10.5 Bridging Fault ATPG ....................... 244
4.11 Other Topics in Test Generation ..................... 246
4.11.1 Test Set Compaction ....................... 246
4.11.2 N -Detect ATPG ........................... 247
4.11.3 ATPG for Acyclic Sequential Circuits .............. 247
4.11.4 IDDQ Testing ............................ 247
4.11.5 Designing a High-Level ATPG .................. 248
4.12 Concluding Remarks ............................ 248
4.13 Exercises ................................... 249
References ...................................... 256


5 Logic Built-In Self-Test 263
Laung-Terng (L.-T.) Wang
5.1 Introduction ................................. 264
5.2 BIST Design Rules ............................. 266
5.2.1 Unknown Source Blocking .................... 267
5.2.1.1 Analog Blocks ..................... 267
5.2.1.2 Memories and Non-Scan Storage Elements .... 268
5.2.1.3 Combinational Feedback Loops ........... 268
5.2.1.4 Asynchronous Set/Reset Signals ........... 268
5.2.1.5 Tristate Buses ..................... 269
5.2.1.6 False Paths ....................... 270
5.2.1.7 Critical Paths ...................... 270
5.2.1.8 Multiple-Cycle Paths ................. 270
5.2.1.9 Floating Ports ..................... 270
5.2.1.10 Bidirectional I/O Ports ................ 271
5.2.2 Re-Timing ............................. 271
5.3 Test Pattern Generation .......................... 271
5.3.1 Exhaustive Testing ........................ 275
5.3.1.1 Binary Counter .................... 275
5.3.1.2 Complete LFSR .................... 275
5.3.2 Pseudo-Random Testing ..................... 277
5.3.2.1 Maximum-Length LFSR ............... 278
5.3.2.2 Weighted LFSR .................... 278
5.3.2.3 Cellular Automata ................... 278
5.3.3 Pseudo-Exhaustive Testing .................... 281
5.3.3.1 Verification Testing .................. 282
5.3.3.2 Segmentation Testing ................. 287
5.3.4 Delay Fault Testing ........................ 288
5.3.5 Summary .............................. 289
5.4 Output Response Analysis ......................... 290
5.4.1 Ones Count Testing ........................ 291
5.4.2 Transition Count Testing ..................... 291
5.4.3 Signature Analysis ......................... 292
5.4.3.1 Serial Signature Analysis ............... 292
5.4.3.2 Parallel Signature Analysis .............. 294
5.5 Logic BIST Architectures .......................... 296
5.5.1 BIST Architectures for Circuits without Scan Chains .... 296
5.5.1.1 A Centralized and Separate Board-Level
BIST Architecture ................... 296
5.5.1.2 Built-In Evaluation and Self-Test (BEST) ..... 297
5.5.2 BIST Architectures for Circuits with Scan Chains ...... 297
5.5.2.1 LSSD On-Chip Self-Test ............... 297
5.5.2.2 Self-Testing Using MISR and Parallel SRSG . . . 298
5.5.3 BIST Architectures Using Register Reconfiguration ..... 298
5.5.3.1 Built-In Logic Block Observer ............ 299
5.5.3.2 Modified Built-In Logic Block Observer ...... 300
5.5.3.3 Concurrent Built-In Logic Block Observer ..... 300
5.5.3.4 Circular Self-Test Path (CSTP) ........... 302
5.5.4 BIST Architectures Using Concurrent Checking
Circuits ............................... 303
5.5.4.1 Concurrent Self-Verification ............. 303
5.5.5 Summary .............................. 304
5.6 Fault Coverage Enhancement ....................... 304
5.6.1 Test Point Insertion ........................ 305
5.6.1.1 Test Point Placement ................. 306
5.6.1.2 Control Point Activation ............... 307
5.6.2 Mixed-Mode BIST ......................... 308
5.6.2.1 ROM Compression .................. 308
5.6.2.2 LFSR Reseeding .................... 308
5.6.2.3 Embedding Deterministic Patterns ......... 309
5.6.3 Hybrid BIST ............................ 309
5.7 BIST Timing Control ............................ 310
5.7.1 Single-Capture ........................... 310
5.7.1.1 One-Hot Single-Capture ............... 310
5.7.1.2 Staggered Single-Capture .............. 311
5.7.2 Skewed-Load ............................ 311
5.7.2.1 One-Hot Skewed-Load ................ 312
5.7.2.2 Aligned Skewed-Load ................. 312
5.7.2.3 Staggered Skewed-Load ............... 314
5.7.3 Double-Capture .......................... 315
5.7.3.1 One-Hot Double-Capture ............... 315
5.7.3.2 Aligned Double-Capture ............... 316
5.7.3.3 Staggered Double-Capture .............. 317
5.7.4 Fault Detection .......................... 317
5.8 A Design Practice .............................. 319
5.8.1 BIST Rule Checking and Violation Repair ........... 320
5.8.2 Logic BIST System Design .................... 320
5.8.2.1 Logic BIST Architecture ............... 320
5.8.2.2 TPG and ORA ..................... 321
5.8.2.3 Test Controller ..................... 322
5.8.2.4 Clock Gating Block .................. 323
5.8.2.5 Re-Timing Logic .................... 325
5.8.2.6 Fault Coverage Enhancing Logic and Diagnostic
Logic .......................... 325
5.8.3 RTL BIST Synthesis ........................ 326
5.8.4 Design Verification and Fault Coverage
Enhancement ........................... 326
5.9 Concluding Remarks ............................ 327
5.10 Exercises ................................... 327
Acknowledgments .................................. 331
References ...................................... 331


6 Test Compression 341
Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba
6.1 Introduction ................................. 342
6.2 Test Stimulus Compression ........................ 344
6.2.1 Code-Based Schemes ....................... 345
6.2.1.1 Dictionary Code (Fixed-to-Fixed) .......... 345
6.2.1.2 Huffman Code (Fixed-to-Variable) ......... 346
6.2.1.3 Run-Length Code (Variable-to-Fixed) ....... 349
6.2.1.4 Golomb Code (Variable-to-Variable) ........ 350
6.2.2 Linear-Decompression-Based Schemes ............ 351
6.2.2.1 Combinational Linear Decompressors ....... 355
6.2.2.2 Fixed-Length Sequential
Linear Decompressors ................ 355
6.2.2.3 Variable-Length Sequential
Linear Decompressors ................ 356
6.2.2.4 Combined Linear and
Nonlinear Decompressors .............. 357
6.2.3 Broadcast-Scan-Based Schemes ................. 359
6.2.3.1 Broadcast Scan .................... 359
6.2.3.2 Illinois Scan ...................... 360
6.2.3.3 Multiple-Input Broadcast Scan ........... 362
6.2.3.4 Reconfigurable Broadcast Scan ........... 362
6.2.3.5 Virtual Scan ...................... 363
6.3 Test Response Compaction ........................ 364
6.3.1 Space Compaction ......................... 367
6.3.1.1 Zero-Aliasing Linear Compaction .......... 367
6.3.1.2 X-Compact ....................... 369
6.3.1.3 X-Blocking ....................... 371
6.3.1.4 X-Masking ....................... 372
6.3.1.5 X-Impact ........................ 373
6.3.2 Time Compaction ......................... 374
6.3.3 Mixed Time and Space Compaction .............. 375
6.4 Industry Practices .............................. 376
6.4.1 OPMISR+ ............................. 377
6.4.2 Embedded Deterministic Test .................. 379
6.4.3 VirtualScan and UltraScan .................... 382
6.4.4 Adaptive Scan ........................... 385
6.4.5 ETCompression .......................... 386
6.4.6 Summary .............................. 388
6.5 Concluding Remarks ............................ 388
6.6 Exercises ................................... 389
Acknowledgments .................................. 390
References ...................................... 391


7 Logic Diagnosis 397
Shi-Yu Huang
7.1 Introduction ................................. 397
7.2 Combinational Logic Diagnosis ...................... 401
7.2.1 Cause–Effect Analysis ....................... 401
7.2.1.1 Compaction and Compression of Fault Dictionary 403
7.2.2 Effect–Cause Analysis ....................... 405
7.2.2.1 Structural Pruning .................. 407
7.2.2.2 Backtrace Algorithm ................. 408
7.2.2.3 Inject-and-Evaluate Paradigm ............ 409
7.2.3 Chip-Level Strategy ........................ 418
7.2.3.1 Direct Partitioning .................. 418
7.2.3.2 Two-Phase Strategy .................. 420
7.2.3.3 Overall Chip-Level Diagnostic Flow ......... 424
7.2.4 Diagnostic Test Pattern Generation ............... 425
7.2.5 Summary of Combinational Logic Diagnosis ......... 426
7.3 Scan Chain Diagnosis ............................ 427
7.3.1 Preliminaries for Scan Chain Diagnosis ............ 427
7.3.2 Hardware-Assisted Method ................... 430
7.3.3 Modified Inject-and-Evaluate Paradigm ............ 432
7.3.4 Signal-Profiling-Based Method ................. 434
7.3.4.1 Diagnostic Test Sequence Selection ........ 434
7.3.4.2 Run-and-Scan Test Application ........... 434
7.3.4.3 Why Functional Sequence? ............. 435
7.3.4.4 Profiling-Based Analysis ............... 437
7.3.5 Summary of Scan Chain Diagnosis ............... 441
7.4 Logic BIST Diagnosis ............................ 442
7.4.1 Overview of Logic BIST Diagnosis ............... 442
7.4.2 Interval-Based Methods ..................... 443
7.4.3 Masking-Based Methods ..................... 446
7.5 Concluding Remarks ............................ 449
7.6 Exercises ................................... 450
Acknowledgments .................................. 453
References ...................................... 454

8 Memory Testing and Built-In Self-Test 461
Cheng-Wen Wu
8.1 Introduction ................................. 462
8.2 RAM Functional Fault Models and Test Algorithms .......... 463
8.2.1 RAM Functional Fault Models .................. 463
8.2.2 RAM Dynamic Faults ....................... 465
8.2.3 Functional Test Patterns and Algorithms ........... 466
8.2.4 March Tests ............................ 469
xvi Contents
8.2.5 Comparison of RAM Test Patterns ............... 471
8.2.6 Word-Oriented Memory ..................... 473
8.2.7 Multi-Port Memory ........................ 473
8.3 RAM Fault Simulation and Test Algorithm Generation ........ 475
8.3.1 Fault Simulation .......................... 476
8.3.2 RAMSES .............................. 477
8.3.3 Test Algorithm Generation by Simulation ........... 480
8.4 Memory Built-In Self-Test ......................... 488
8.4.1 RAM Specification and BIST Design Strategy ......... 489
8.4.2 BIST Architectures and Functions ............... 493
8.4.3 BIST Implementation ....................... 495
8.4.4 BRAINS: A RAM BIST Compiler ................ 500
8.5 Concluding Remarks ............................ 508
8.6 Exercises ................................... 509
Acknowledgments .................................. 513
References ...................................... 513


9 Memory Diagnosis and Built-In Self-Repair 517
Cheng-Wen Wu
9.1 Introduction ................................. 518
9.1.1 Why Memory Diagnosis? ..................... 518
9.1.2 Why Memory Repair? ....................... 518
9.2 Refined Fault Models and Diagnostic Test Algorithms ........ 518
9.3 BIST with Diagnostic Support ....................... 521
9.3.1 Controller .............................. 521
9.3.2 Test Pattern Generator ...................... 523
9.3.3 Fault Site Indicator (FSI) ..................... 524
9.4 RAM Defect Diagnosis and Failure Analysis ............... 526
9.5 RAM Redundancy Analysis Algorithms ................. 529
9.5.1 Conventional Redundancy Analysis Algorithms ........ 529
9.5.2 The Essential Spare Pivoting Algorithm ............ 531
9.5.3 Repair Rate and Overhead .................... 535
9.6 Built-In Self-Repair ............................. 537
9.6.1 Redundancy Organization .................... 537
9.6.2 BISR Architecture and Procedure ................ 538
9.6.3 BIST Module ............................ 541
9.6.4 BIRA Module ............................ 542
9.6.5 An Industrial Case ......................... 545
9.6.6 Repair Rate and Yield ...................... 548
9.7 Concluding Remarks ............................ 552
9.8 Exercises ................................... 552
Acknowledgments .................................. 553
References ...................................... 553

10 Boundary Scan and Core-Based Testing 557
Kuen-Jong Lee
10.1 Introduction ................................ 558
10.1.1 IEEE 1149 Standard Family .................. 558
10.1.2 Core-Based Design and Test Considerations ......... 559
10.2 Digital Boundary Scan (IEEE Std. 1149.1) .............. 561
10.2.1 Basic Concept .......................... 561
10.2.2 Overall 1149.1 Test Architecture and Operations ...... 562
10.2.3 Test Access Port and Bus Protocols .............. 564
10.2.4 Data Registers and Boundary-Scan Cells .......... 565
10.2.5 TAP Controller .......................... 567
10.2.6 Instruction Register and Instruction Set ........... 569
10.2.7 Boundary-Scan Description Language ............ 574
10.2.8 On-Chip Test Support with Boundary Scan ......... 574
10.2.9 Board and System-Level Boundary-Scan Control
Architectures ........................... 576
10.3 Boundary Scan for Advanced Networks (IEEE 1149.6) ....... 579
10.3.1 Rationale for 1149.6 ....................... 579
10.3.2 1149.6 Analog Test Receiver .................. 581
10.3.3 1149.6 Digital Driver Logic ................... 581
10.3.4 1149.6 Digital Receiver Logic ................. 582
10.3.5 1149.6 Test Access Port (TAP) ................. 584
10.3.6 Summary ............................. 585
10.4 Embedded Core Test Standard (IEEE Std. 1500) .......... 585
10.4.1 SOC (System-on-Chip) Test Problems ............ 585
10.4.2 Overall Architecture ....................... 587
10.4.3 Wrapper Components and Functions ............. 589
10.4.4 Instruction Set .......................... 597
10.4.5 Core Test Language (CTL) ................... 601
10.4.6 Core Test Supporting and System Test Configurations . . 603
10.4.7 Hierarchical Test Control and Plug-and-Play ........ 606
10.5 Comparisons between the 1500 and 1149.1 Standards ....... 610
10.6 Concluding Remarks ........................... 611
10.7 Exercises .................................. 612
Acknowledgments ................................. 614
References ..................................... 614

11 Analog and Mixed-Signal Testing 619
Chauchin Su
11.1 Introduction ................................ 619
11.1.1 Analog Circuit Properties .................... 620
11.1.1.1 Continuous Signals ................. 621
xviii Contents
11.1.1.2 Large Range of Circuits .............. 621
11.1.1.3 Nonlinear Characteristics ............. 621
11.1.1.4 Feedback Ambiguity ................ 622
11.1.1.5 Complicated Cause–Effect Relationship ..... 622
11.1.1.6 Absence of Suitable Fault Model ......... 622
11.1.1.7 Requirement for Accurate Instruments for
Measuring Analog Signals ............. 623
11.1.2 Analog Defect Mechanisms and Fault Models ........ 623
11.1.2.1 Hard Faults ...................... 625
11.1.2.2 Soft Faults ...................... 625
11.2 Analog Circuit Testing .......................... 627
11.2.1 Analog Test Approaches .................... 627
11.2.2 Analog Test Waveforms ..................... 629
11.2.3 DC Parametric Testing ..................... 631
11.2.3.1 Open-Loop Gain Measurement .......... 632
11.2.3.2 Unit Gain Bandwidth Measurement ....... 633
11.2.3.3 Common Mode Rejection Ratio Measurement . 634
11.2.3.4 Power Supply Rejection Ratio Measurement . . 635
11.2.4 AC Parametric Testing ..................... 635
11.2.4.1 Maximal Output Amplitude Measurement .... 636
11.2.4.2 Frequency Response Measurement ........ 637
11.2.4.3 SNR and Distortion Measurement ........ 639
11.2.4.4 Intermodulation Distortion Measurement .... 641
11.3 Mixed-Signal Testing ........................... 641
11.3.1 Introduction to Analog–Digital Conversion ......... 642
11.3.2 ADC and DAC Circuit Structure ................ 644
11.3.2.1 DAC Circuit Structure ............... 646
11.3.2.2 ADC Circuit Structure ............... 646
11.3.3 ADC/DAC Specification and Fault Models .......... 647
11.3.4 IEEE 1057 Standard ...................... 652
11.3.5 Time-Domain ADC Testing ................... 654
11.3.5.1 Code Bins ....................... 654
11.3.5.2 Code Transition Level Test (Static) ........ 655
11.3.5.3 Code Transition Level Test (Dynamic) ...... 655
11.3.5.4 Gain and Offset Test ................ 656
11.3.5.5 Linearity Error and Maximal Static Error .... 657
11.3.5.6 Sine Wave Curve-Fit Test .............. 658
11.3.6 Frequency-Domain ADC Testing ............... 658
11.4 IEEE 1149.4 Standard for a Mixed-Signal Test Bus ......... 658
11.4.1 IEEE 1149.4 Overview ..................... 659
11.4.1.1 Scope of the Standard ............... 660
11.4.2 IEEE 1149.4 Circuit Structures ................ 661
11.4.3 IEEE 1149.4 Instructions ................... 665
11.4.3.1 Mandatory Instructions .............. 665
11.4.3.2 Optional Instructions ................ 665
Contents xix
11.4.4 IEEE 1149.4 Test Modes .................... 666
11.4.4.1 Open/Short Interconnect Testing ......... 666
11.4.4.2 Extended Interconnect Measurement ...... 667
11.4.4.3 Complex Network Measurement ......... 671
11.4.4.4 High-Performance Configuration ......... 672
11.5 Concluding Remarks ........................... 673
11.6 Exercises .................................. 673
Acknowledgments ................................. 676
References ..................................... 677


12 Test Technology Trends in the Nanometer Age 679
Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang
12.1 Test Technology Roadmap ........................ 680
12.2 Delay Testing ............................... 685
12.2.1 Test Application Schemes for Testing Delay Defects .... 686
12.2.2 Delay Fault Models ....................... 687
12.2.3 Summary ............................. 690
12.3 Coping with Physical Failures, Soft Errors,
and Reliability Issues ........................... 692
12.3.1 Signal Integrity and Power Supply Noise .......... 692
12.3.1.1 Integrity Loss Fault Model ............. 693
12.3.1.2 Location ....................... 694
12.3.1.3 Pattern Generation ................. 694
12.3.1.4 Sensing and Readout ................ 695
12.3.2 Parametric Defects, Process Variations, and Yield ..... 696
12.3.2.1 Defect-Based Test .................. 697
12.3.3 Soft Errors ............................ 698
12.3.4 Fault Tolerance ......................... 701
12.3.5 Defect and Error Tolerance .................. 705
12.4 FPGA Testing ............................... 706
12.4.1 Impact of Programmability .................. 706
12.4.2 Testing Approaches ....................... 708
12.4.3 Built-In Self-Test of Logic Resources ............. 708
12.4.4 Built-In Self-Test of Routing Resources ........... 709
12.4.5 Recent Trends .......................... 710
12.5 MEMS Testing ............................... 711
12.5.1 Basic Concepts for Capacitive MEMS Devices ....... 711
12.5.2 MEMS Built-In Self-Test .................... 713
12.5.2.1 Sensitivity BIST Scheme .............. 713
12.5.2.2 Symmetry BIST Scheme .............. 713
12.5.2.3 A Dual-Mode BIST Technique ........... 714
12.5.3 A BIST Example for MEMS Comb Accelerometers .... 716
12.5.4 Conclusions ........................... 719
xx Contents
12.6 High-speed I/O Testing .......................... 719
12.6.1 I/O Interface Technology and Trend ............. 720
12.6.2 I/O Testing and Challenges ................... 724
12.6.3 High-Performance I/O Test Solutions ............ 725
12.6.4 Future Challenges ........................ 726
12.7 RF Testing ................................. 728
12.7.1 Core RF Building Blocks .................... 729
12.7.2 RF Test Specifications and Measurement Procedures . . . 730
12.7.2.1 Gain .......................... 730
12.7.2.2 Conversion Gain ................... 731
12.7.2.3 Third-Order Intercept ................ 731
12.7.2.4 Noise Figure ..................... 733
12.7.3 Tests for System-Level Specifications ............ 733
12.7.3.1 Adjacent Channel Power Ratio .......... 733
12.7.3.2 Error Vector Magnitude, Magnitude Error, and
Phase Error ..................... 734
12.7.4 Current and Future Trends .................. 735
12.7.4.1 Future Trends .................... 736
12.8 Concluding Remarks ........................... 737
Acknowledgments ................................. 738
References ..................................... 738

Index 751

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