1. Current: Subcircuit Pin
Syntax
ISUB(X****.****)
Example
.PROBE ISUB(X1.PIN1) //note: PIN1 is subckt pin name defined in the subckt header
2.
Output Internal Module Variables (HSPICE only)
Verilog-A internal variables, by default, are hidden from output. However,
module variables with a description or units attribute, or both, are known as
output variables, and HSPICE provides access to their ...
1. Current: Subcircuit Pin
Syntax
ISUB(X****.****)
Example
.PROBE ISUB(X1.PIN1) //note: PIN1 is subckt pin name defined in the subckt header
2.
Output Internal Module Variables (HSPICE only)
Verilog-A internal variables, by default, are hidden from output. However,
module variables with a description or units attribute, or both, are known as
output variables, and HSPICE provides access to their values; for example,
suppose a module for a MOS transistor with the following declaration at module
scope provides the output variable cgs:
(* desc="gate-source capacitance", units="F" *) real cgs;
The cgs module variable can be printed just like a normal parameter variable.
Syntax
Instance:internal_variable
Example
.print xva_vco:freq
This example outputs internal variable frequency value of Verilog-A instance
xva_vco.