本帖最后由 nanke 于 2020-12-28 18:24 编辑
JEDEC JEP172A-2015也就是
DISCONTINUING USE OF THE MACHINE MODEL FOR DEVICE ESD QUALIFICATION
Over the last several decades the so called "machine model" (aka MM) and its application to the required ESD component qualification has been grossly misunderstood. The scope of this JEDEC document is to present evidence to discontinue use of this particular model stress test without incurring any reduction in the IC component's ESD reliability for manufacturing. In this regard, the document's purpose is to provide the necessary technical arguments for strongly recommending no further use of this model for IC qualification. The published document should be used as a reference to propagate this message throughout the industry.
文章里说HBM和CDM的机制已完全弄清,MM还不确定。也没提有什么可用的simulator/
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