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工作职责: a, In charge of 3D NAND flash chip level functional verification b, Understand the design architecture spec and develop test plan c, Build and maintain UVM testbench, create directive and random sequence d, Develop functional coverage and analyze the result e. simulate, analyze and debug current chip designs 任职资格: a, Computer Science, Electrical Engineering, Micro-Electronics related majors are preferred b, 3+ years design verification work experience(BSEE,MS) c, Good at Verilog / SystemVerilog / SystemC / UVM d, Good at "script"s, Python or perl is a plus e, Solid knowledge of 3D NAND protocol and architecture is a plus f, Strong ability for problem analyzing & solving g, Good communication skill & team working
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