systemverilog中断言until的语法有大神介绍一下么？

suosuo0624

如题所示

suosuo0624

自己顶一下，求大神围观

dogor1

The property until checks that the antecedent 'a' is true, for every clock cycle until (but not including) consequent 'c' is true. Using the example

1. ap_until: assert property (@(posedge clk) a until c);
   

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, this assertion will pass iff a is true for N clock cycles and is followed by c; 'a' has to be false before 'c' is true, because `until` property is not overlapping.

If you still have doubts, either check the IEEE 1800-2012 for the formal semantics on the property, or let me know so we can create a small example.

anpengfei

3l正解

suosuo0624

dogor1 发表于 2020-8-20 03:38
The property until checks that the antecedent 'a' is true, for every clock cycle until (but not incl ...

谢谢大神

dullman

除了until，还有一个until_with也比较常用。
二者的区别时，一个包含了重叠，一个不用重叠。
对于下面波形（从左到右表示电平变化的顺序）:
a:-1-1-1-0-0-0
b:-0-0-0-1-1-1
a until b = true 但是 a until_with b = false

波形改为:
a:-1-1-1-1-0-0
b:-0-0-0-1-1-1
a until b = true 且 a until_with b = true