【上海张江初创AI芯片公司】【内推】急招！软件团队，SOC 设计/实现职位

清扬如昀 · 发表于 2020-7-30 21:02:10

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本帖最后由清扬如昀于 2020-7-31 10:55 编辑

上海张江知名初创AI芯片公司，急招！待遇优厚！不强制加班！感兴趣的小伙伴可以邮件联系我： Bermuda0527@163.com

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软件职位

1. 计算框架团队（GPGPU方向）

1.1 工作内容
a. 基于自研GPGPU适配/优化/维护常用AI计算框架TensorFlow、PyTorch、MXNet等。
b. 实现易扩展、高性能、大规模的AI模型训练系统，发挥自研GPGPU的优越性。
c. 基于自研芯片设计构建高性能推理引擎。
1.2 资历要求
a. 计算机硕士+1年相关工作经验，或计算机学士+3年工作经验
b. 具有计算机相关领域背景，熟悉AI领域更好。
c. 熟练使用Python/C/C++编程。
d. 熟悉CUDA编程。
e. 对TensorFlow/PyTorch实现原理熟悉、熟悉底层代码的实现。
f. 对分布式计算/训练框架有开发经验。
g. 熟悉TensorRT/TVM等推理引擎，了解原理。
h. 有良好的的团队合作精神和沟通能力

2. 函数库团队
2.1 工作内容
a. 为异构计算加速库编写CUDA Kernel（如BLAS, FFT, DNN and Sparse）
b. 定义并实现加速库API
c. 算法优化及性能调优
2.2 资历要求
a. 计算机硕士+1年相关工作经验，或计算机学士+3年工作经验
b. 熟悉C/C++
c. 熟悉CUDA Kernel编程
d. 熟悉算法常用的基本数学原理
e. 熟悉CPU/GPU计算体系架构
f. 了解主流AI框架和DNN模型
g. 有良好的的团队合作精神和沟通能力

3. 编译器团队
3.1 工作内容
a. 研发CUDA兼容的、基于LLVM的编译器
b. 实现与CUDA PTX指令兼容的编译器和运行环境
c. 测评和优化编译器的性能，为程序生成最优的机器指令
3.2 资历要求
a. 计算机硕士+1年相关工作经验，或计算机学士+3年工作经验
b. 熟悉C/C++
c. 熟悉CUDA或OpenCL
d. 熟悉CPU/GPU计算体系架构
e. 有LLVM工作经验者优先
f. 有在CUDA PTX上从事研发或了解PTX内部实现者优先
g. 有良好的的团队合作精神和沟通能力

4. 驱动团队
4.1 工作内容
a. 研发GPGPU用户态及内核态驱动
b. 协助性能团队分析并优化产品性能
c. 协助DV，硬件团队完成产品定义以及芯片功能验证
d. 日常驱动维护以及Debug
e. 内部测试及开发工具，以帮助完成芯片验证及后期Debug
4.2 资历要求
a. 计算机硕士+1年相关工作经验，或计算机学士+3年工作经验
b. 熟悉C/C++
c. 了解设备驱动开发，GPU驱动经验尤佳
d. 熟悉操作系统架构(Linux/Unix/Windows)
e. 熟悉计算机体系结构
f. 有芯片Bringup项目经验者优先
g. 熟悉系统及驱动性能调优
h. 有良好的的团队合作精神和沟通能力

5. 性能团队
5.1 工作内容
a. 对自研芯片的软件栈进行性能评价、分析
b. 定位性能问题，提供性能优化方案
c. 构建针对自研芯片系统软件栈的性能Benchmark
d. 调研最新的性能相关开源技术，为后期的性能优化工作提供技术保障
e. 对市场上主流异构计算平台进行性能评价、分析和调研，对优化方法等进行技术储备
f. 基于自研芯片软件栈和TVM等开源项目，构建面向深度学习的推理加速引擎
g. GPU虚拟化相关性能调查及评价、分析
5.1 资历要求
a. 计算机硕士+1年相关工作经验，或计算机学士+3年工作经验
b. 熟悉C/C++、Python、Shell编程
c. 熟悉主流AI框架和DNN模型
d. 具有Linux及服务器性能相关工作经验
e. 具有异构性能优化经验
f. 熟悉CUDA者优先
g. 熟悉LLVM/TVM者优先
h. 有良好的的团队合作精神和沟通能力

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硬件职位

1. Deep Learning Verification Engineer
Job Description
1.1 Responsibilities:
a. Understand and closely discuss with architects / designers for hardware arch and micro-arch
b. Make up Block / IP / SOC level verification plan (methodology / testbench / testplan / coverage / ...) and improve cross environment reuse
c. Develop and debug testbench, tests and drive verification closure with coverage and other sign-offs
d. Develop and verify reference C-model for functional and performance purpose
e. Develop flows / tools to improve work efficiency
f. Communicate with software team for SW-HW interaction and code sharing
1.2 Qualifications:
a. Computer Science, Electrical Engineering, Micro-Electronics related majors are preferred
b. Good at Verilog/SystemVerilog/UVM/C/C++/Python
c. Good background in computer architecture is a plus
d. Familiarity with machine learning and deep learning is a plus
e. Familiarity with GPU computing (CUDA, OpenCL, cuDNN, TensorRT) is a plus
f. Good problem-solving ability is desired
g. Good communication skill is desired
h. Good team working is desired

2. System Validation Engineer – PCIe
Job Description
2.1 Resdonsibilities:
a. Working closely with IP design team to define PCIe validation methodology;
b. Develop silicon level PCIe test plan, working with validation tools or test script to verify all PCIe features
c. Attend ASIC bring-up and validation test, execute all PCIe feature test plans and track to be successfully enabled;
d. To be responsible for system level issue debugging;
e. Develop automation tool/script to improve memory test efficiency;
f. Provide technical support for both internal and external customers application
2.2 Qualifications:
a. Bachelor or Master in EE/CS or equivalent is required
b. Knowledge on PCI/PCI express architecture and hands-on experience with test equipment using
c. Familiar with high speed signal integrity theory and test methodology;
d. Strong skills in system level issue debug and analyzing
e. Experience in software development with script languages such as Perl, or Python;
f. A quick learner for new technologies and team player

3. ASIC Design Engineer
Job Description
3.1 Job Responsibilities:
a. Develop micro-architecture, write micro-architecture spec and other documents
b. Write RTL code, meet the function target and have good performance/power/area efficiency
c. Apply low power, DFT, DFD and other digital design techniques
d. Work with DV team to improve test plan and debug failed tests
e. lean Lint, timing and other issues
f. Participate in silicon debugging
3.2 Qualifications::
a. Master in electrics or computer engineering.
b. Expert of Verilog RTL design
c. Experience of large digital ASIC project
d. Familiar with front-end EDA tools and flows
e. Programming skill in SystemVerilog, C/C++, perl, Tcl/tk, Python, etc. is preferred
f. Familiar with Linux Environment
g. Good communication in both Chinese and English
h. Good team player and strong sense of responsibility
i. Strong problem solving skills
j. Have one or some of the following design experience: memory controller, graphics, fabric, microprocessor.

4.Staff SOC Design Engineer (SCU HW – CPU direction)
Job Description
4.1 Job Responsibilities:
a. Be responsible for block RTL code development and integration for system control unit. Focus on RISC-V ( or ARM CPU) IP integration and related sub-system blocks' coding;
b. Work with architect team (SOC/IP) to define block feature;
c. Work with SOC DV team to define the testplan;
d. Work with implementation team to close the timing;
e. Integrate block design into SOC;
f. Support silicon bringup.
4.2 Qualifications::
a. Be familiar with ASIC design flow and RTL coding, be able to do optimization for area, performance and power;
b. Be familiar with system boot, power control and thermal control;
c. Be familiar with asynchronous design;
d. Be familiar with SOC architecture, has experience in the protocol such as AXI, AHB or APB;
e. Be familiar with the external communication interface such as I2C, SPI, PCIe are plus;
f. Be familiar with the data transaction control such as DMA is a plus;
g. Self-motivated, proactive, team work and achievement oriented;
h. Good communication skill and work well with cross-functional teams and technical leadership are big plus.

5.DFT Engineer
Job Description
5.1 Job Responsibilities:
a. The candidate is expected to be responsible for following tasks:
b. Participate in SOC full Chip DFT feature and architecture definition
c. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
d. Generate DFT related timing constraints and work for timing closure
e. Develop and verify high coverage and cost-effective test patterns for the production test 6. Evaluate and establish the advanced DFT tools and flow
5.2 Qualifications::
a. 8+ years’s experience for Bachelor or 5+ years for Master in DFT design and verification, test pattern development
b. Good Knowledge of Scan/ATPG, MBIST and boundary scan and other DFT techniques
c. Good Knowledge of industry DFT tools like DFTMax, TetraMax ,TestKompress, FastScan, Tessent Mbist, SMS etc
d. Good knowledge of digital SoC/ASIC design, including STA, verification and RTL coding
e. Proficient in hardware description languages such as Verilog, System Verilog and VHDL
f. Good Knowledge of script language, such as Tcl, Python, Perl
g. Good English communication skills
h. Strong commitment to schedule and work quality, good team player