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1. 资深/主任 IC设计工程师（ISP，图像信号处理器） 职位描述： 理解图像处理算法进行微架构设计和设计文档, 负责模块和ISP 顶层的RTL实现，优化及验证，并进行设计流程检查和FPGA测试 职位要求: l 三年以上数字IC 设计经验，硕士以上学历及相关专业，熟练掌握verilog编程l 了解视频或者图像处理知识 l 具备丰富的asic电路设计项目经验，包括设计文档，微架构设计和RTL 实现l 掌握设计流程，比如综合约束，时序检查，lint 、CDC、DFT等l 具备ISP项目经验者优先考虑，比如3D降噪，HDR，白平衡，图像增强相关经验 l 积极主动的发现和解决工作中遇到各种问题, 具有良好的团队合作意识
工作地点：上海 张江高科 Senior/Staff Engineer of ASIC Design (Image Signal Processor) Responsibilities: Design micro-architecture for image processing algorithms, spec definition, Block and top level RTL implementation, optimization and verification, Design flow and FPGA validation. Requirements: l 3+ years hands-on ASIC design, master degree and above with related major, programming skills in Verilog hdl. l Knowledge of Image or video processing. l Experience of ASIC design (including specification, micro-architecture, and RTL implementation). l Be familiar with design flow (Synthesis, Lint, CDC, DFT, and etc.). l Experience of Image processor design, such as 3D noise reduction, HDR, white balance, image enhancer will be a plus. l Highly motivated and skillful at solving difficult technical problems.
Location：Shanghai
2. 资深/主任芯片验证工程师 职位描述： l 负责ISP IP的模块和系统验证 l 根据设计规范,制定模块级/子系统级/系统级的测试计划，分解和提取对应的测试点 l 和设计工程师紧密配合，正确理解设计意图和客户要求，编写出高效高质量的测试用例 l 负责验证平台的搭建和维护，验证用例的编写以及验证执行，覆盖率收集 职位要求： l 3年以上ASIC 验证工作经验，硕士以上学历及相关专业 l 熟练掌握验证语言（systemverilog），熟悉AISC 验证流程 l 熟练掌握UVM 验证方法学。使用UVM独立搭建2个以上的系统级验证环境 l 至少掌握Perl、Python、TCL 、Makefile等脚本的语言的一种 l 熟悉ISP 图像处理算法者优先 l 积极主动的发现和解决工作中遇到各种问题, 具有良好的团队合作意识 工作地点：上海 张江高科
Senior/Staff ASIC Design verification engineer Responsibilities: l In charge of ISP module or ISP system verification l Write module/Subsystem/System level test-plan and extract test-point from design SPEC l Work closely with designers. Understand customer’s requirements and design purpose, write out high efficient and excellent test case l Setup and maintain test-bench. Write test case and run regression, collect function coverage and code coverage. Requirements: l 3+ years hands-on ASIC verification, master degree and above with related major l Familiar with verification language（systemverilog）and ASIC verification flow l Skillful at UVM methodology, and setup 2+ system level test bench with UVM l At least be familiar with one script (Perl/Python/TCL/Makefile) l Knowledge of ISP processing is a plus l Highly motivated to explore and solve difficult problems, good communication and teamwork
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发表于 2020-6-10 14:54:41
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