上海深圳数字设计职位招聘

daisyyang

上海 深圳数字设计职位招聘，power方向
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Power digital Design Engineer-SH
Requirement:
BSEE at least 5 years or MSEE 2 year of related experiences.
Solid/outstanding Knowledge of Verilog, simulations, digital analysis and synthesizing, timing and digital logic circuits
Debug from the Verilog code, system level, schematic, netlist and down to the component level.
Familiarity with digital IC design flow and tools (NC, DC, Encounter, etc)
Demonstrated strong analytical and problem-solving skills.
Familiar with FPGA verification and bench test.
Excellent verbal and written communication skills both in English and Chinese.
Ability to work in teams and collaborate effectively with people in different functions.
Bench automation test experiences (such as LabView, Python) is plus.
Must have experience with I2C bus design
Must have Place and Route experience



Responsibility:
Analyze the datasheet and IC applications, to create the digital design specs and functions, making design schedules, finish the ASIC design, and layout Place and Route.，
Interface to AE, TE, PE to create full digital design flow, including: Verilog coding, synthesizing, timing, clock tree, mixed signal simulations, AMS simulations, test, bench validations, FPGA tests, etc.
Intensive involvement in design-in activities with customers including providing system design proposal, preparing customized demo, on-site technical support, customer failure analysis support, etc.
Can do full chip simulations and create test codes, work with test engineer on the ATE tests. Work with AE and work alone for product validations and debug。
Validation work of IC product and generate test evaluation report.
Create digital test note, white paper and datasheet for the products.
Co-work with product engineers and IC designers to finish new product design.