有问题求助，vcs+verdi+uvm仿真出现如下错误

time_hunter

*design* DebussyLib (btIdent Verdi3_K-2015.09-SP1-1)
Command arguments:
    +define+verilog
    +v2k
    -sverilog
    +incdir+/uvm_lianxi/hello_demo+../../../home/uvm/uvm-1.1a/src
    ../../../home/uvm/uvm-1.1a/src/uvm.sv
    ../../../home/uvm/uvm-1.1a/src/dpi/uvm_dpi.cc
    -CFLAGS
*Warning* Unknown argument -CFLAGS

    +systemverilogext+sv
    +verilog2001ext+v
    hello_tb_top.sv


*Error* Syntax error at #
"../../../home/uvm/uvm-1.1a/src/dpi/uvm_dpi.cc", 29:

*Error* Syntax error at {
"../../../home/uvm/uvm-1.1a/src/dpi/uvm_dpi.cc", 30:

*Error* Syntax error at #
"../../../home/uvm/uvm-1.1a/src/dpi/uvm_dpi.cc", 31:

*Error* Syntax error at #
"../../../home/uvm/uvm-1.1a/src/dpi/uvm_dpi.cc", 33:

*Error* Syntax error at #
"../../../home/uvm/uvm-1.1a/src/dpi/uvm_dpi.cc", 34:

*Error* Syntax error at #
"../../../home/uvm/uvm-1.1a/src/dpi/uvm_dpi.cc", 35:

*Error* Syntax error at #
"../../../home/uvm/uvm-1.1a/src/dpi/uvm_dpi.cc", 37:

*Error* Syntax error at }
"../../../home/uvm/uvm-1.1a/src/dpi/uvm_dpi.cc", 38:

*Error* Syntax error at #
"../../../home/uvm/uvm-1.1a/src/dpi/uvm_dpi.cc", 39:
Highest level modules:
hello_tb_top

Total        9 error(s),   1 warning(s)

luke_h

你好，请问你解决了吗？