How unmatched impedance at the clock input of an RF ADC affects SNR and jitter

liuliu7812

Modern high-speed data acquisition systems,such as phased-array radars or high-speed digitizers, continue to push higher both the bandwidth and input-frequency requirementsn without any sacrifice of dynamic range performance. System designers need to deliver the highest possible signal-to-noise ratio (SNR) in order to optimize system performance down to a tenth of a decibel. However, it is well known that as input frequencies increase, the analog-to-digital converter (ADC) SNR becomes increasingly sensitive to the sampling-clock’s timing uncertainty— or jitter. This applies to slower speed but high-precision ADCs with 16-bit resolution or more, and very high SNR. This situation also applies to high-speed 12- and 14-bit
ADCs that have a wide bandwidth front-end
to sample signals at multiple gigahertz. The
SNR degradation follows a well known formula of:
SNR = 20log(2π × fIN × tJitter),
where tJitter is the combination of both external and internal
aperture jitter. Figure 1 shows SNR dependency on the
input frequency and the total amount of clock jitter for an
ADC with 76-dB thermal noise

dcircuit

thanks

kayjep

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dannymu

谢谢

jingxin_xd

感谢分享！！！

amigo.change

yimei_018

Thanks sharing.
TI application note

dannymu

谢谢

dannymu

谢谢

AlexKe

谢谢分享