第二轮融资的AI 公司AI designer 招聘（非猎头，内部员直接推荐）工）

wangyukan · 发表于 2019-7-5 21:56:00

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公司现在已经进行完了第二轮融资，现在招聘不同级别的 AI designer， JD 如下
如果感兴趣请发简历到 yukan.wang@enflame-tech.com

AI Processor Designer

Location：Shanghai

Job Description

· You will join AI processor coredesign team as key ASIC designer, focusing on delivery of micro-architectmodeling/profiling/investigation, design spec creation, RTL design,verification, optimization for power/performance/area, etc..

· You will have the chance to workwith the design team, chip architect and SW to define next-gen cloud side AIchip's AI processor, its memory hierarchy and programming model, focusing onimproving programmability/performance/power/area.

Position's Technical Requirement

· Master or higher degree in EE/CSwith expertise in computer architecture

· Five years or more digital designexperience especially CPU or GPU, good at micro-architect design skills

· Solid skills in all digital designaspects, including congestion fixing, performance design skills and tuning,design for low power, etc.

· Familiar with C/C++ and processormodeling is a good plus

· Design experience on highperformance memory system or load/store unit is a good plus

· Design experience on AI domainchip/solid AI domain architect knowledge is a good plus

· Design experience on vector/SIMD/DSPprocessor is a good plus

· Good understanding onproperty/assertion based formal verification is a good plus

· Experience in multi-core/many coresystem is a good plus

Position's Cultural Requirement

· Strong ownership mindset andproactivity

· Great mindset in teamwork spirit andfocus on team delivery first

· Honest, direct, open minded and withgreat communication skills to collaborate with people from diversebackgrounds/companies in a fresh environment

· Strong wishes to contribute andalign with teammates on continuous investigation and improvement for yourselfand the team

AI Processor Designer JD2

Position's Technical Requirement

· Master or higher degree in EE/CSwith expertise in computer architecture, with great potential

· 1~2 year or more digital designexperience especially CPU or GPU, good at micro-architect design skills

· Good at script programming, such asshell, ruby, makefile, etc.

· Good at EDA flow such as synthesis,power analysis, trial floorplan, etc. for quick design evaluation

· Low power design experience is agood plus

· Design experience onCPU/GPU/vector/SIMD/DSP processor is a good plus

· Familiar with C/C++ and processormodeling is a good plus

Position's Cultural Requirement

· Strong ownership mindset andproactivity

· Great mindset in team work spiritand focus on team delivery first

· Honest, direct, open minded, matureand with great communication skills to collaborate with people from diversebackgrounds/companies in a fresh environment

· Strong wishes to contribute andalign with teammates on continuous investigation and improvement for yourselfand the team

Job Description

· You will join AI processor coredesign team as key ASIC designer, focusing on delivery of micro-architectmodeling/profiling/investigation, design spec, RTL design, verification,integration, infrastructure, optimization for power/performance/area, etc..

wangyukan · 发表于 2019-7-8 20:35:53

update

wangyukan · 发表于 2019-7-10 20:56:01

update

wangyukan · 发表于 2019-9-27 14:18:32

还在继续招聘

wangyukan · 发表于 2019-9-27 14:21:01

增加 PCIE designer 岗位
1) Responsibility:
• Subsystem features define and review.
• Subsystem design implementation, including the spec written and RTL coding.
• Subsystem level synthesis and timing closure.
• Subsystem level performance and power analysis
• Integrate components to subsystem, including the RTL and SDC, etc.
• Integrate subsystem to SOC, including the RTL and SDC, etc.
• Subsystem/SOC level CDC, Lint check and clean
• Working with Verification engineer closely on functional and performance verification.
• Working with the SOC Front-end team and PD team closely on the SOC implementation.
• Software, modeling, firmware design and verification support.
• Post silicon verification support

2) Requirement:
• 3+ year PCIe controller (Gen3/Gen4/Gen5) or Serdes design (IP or integration) experience;
• In-depth knowledge of PCIe protocol and system architecture.
• PCIe lab debug experience is highly preferred.
• Strong RTL coding and verification capability.
• Hands-on experience on ASIC simulation/implementation flow and corresponding tools: VCS, Spyglass, DC, PT…
• Familiar with scripting languages like Perl/Makefile/Python …
• Strong problem solver, communicator and team player.

wangyukan · 发表于 2019-9-27 14:22:17

增加 PCIE DV 岗位
1) Responsibility:
• Working with sub-system design engineer closely on PCIe/interconnect sub-system functional and performance verification.
o Subsystem verification plan
o Subsystem verification environment setup and maintain, including scoreboard , predictor, monitor
o Subsystem testcase generate, test running and debug
o Subsystem Regression environment setup and maintain
o Subsystem system function coverage environment setup and coverage measures
o Subsystem system Code coverage environment setup and coverage measures
• Working with system team to verify functional and performance of the interconnect among Chips.
• Software/firmware/post silicon verification support.
• Sub-system gate level simulation
• Sub-system level power analysis

2) Requirement:
• BS degree or equivalent practical experience.
• Experience with UVM/OVM/VMM verification methodology
• Experience with the full verification life cycle and experience with functional coverage
• Knowledge on PCIE system or AXI system is highly preferred.
• Familiar with scripting languages like Perl/Makefile/Python…
• Strong problem solver, communicator and team player.