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[招聘] Cadence 6月份最新内推职位

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发表于 2019-6-3 00:57:41 | 显示全部楼层 |阅读模式

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符合條件的可嘗試,内推成功率大

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简历请投递至 3114835608@qq.com
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Title: Lead Design Engineer (Logic Implementation / Synthesis / STA)
Location: SH


Position Description:
- In charge of DDR IP logic design Implementation.
- Daily duties include: RTL coding(plus), Logic Synthesis(must), Static Timing Analysis(must).
- hdl language Knowledge, like verilog or vhdl is necessary.
- C/C++/perl/tcl/csh/python, UNIX, Linux experience are plus.
- Excellent analytical and problem-solving skills. Quick learner-able to learn and apply technical and complex topics.
- Excellent communication skills and the uncanny ability in a cooperative team environment are required.
- Self-motivated, result-oriented, can take ownership and follow-through on tasks.
Essential Qualifications:
- Master degree with 3~6 years’experience
- Major in Micro-electronics, Electronic Engineering, Computer Science, Information Technology or equivalent
- Ability to work effectively alone or as well as in the team.
- Essential that the individual demonstrates strong communication, verbal and written
- Requires good communication skills in English.

 楼主| 发表于 2019-6-15 13:12:16 | 显示全部楼层
adding

Title: Lead/Principal Front-end Design Engineer (RTL Coding)  数字前端设计
Location: SH/BJ


Position Description:
Deliver/implement DDR IP. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.

Specific duties include:
- Be responsible for building and leading a high-performance IC design team, owning the IC micro-architecture, package and test platform development, refining the EDA design flow
- Proficiency in logic design, simulation, synthesis, STA and testing
- Proficiency in Verilog and its simulation environment
- Good knowledge of IC design

Position Requirements:
1. Essential Qualifications: Must have BS degree with 4+ years of applicable experience, MS degree with 2+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
2. Essential that the individual demonstrates strong communication, verbal and written.
3. Requires good communication skills in English.
 楼主| 发表于 2019-6-6 20:20:40 | 显示全部楼层
Still open
 楼主| 发表于 2019-6-22 19:11:46 | 显示全部楼层
Still open
发表于 2019-6-26 16:27:14 | 显示全部楼层
深圳的有吗
 楼主| 发表于 2019-7-11 02:24:33 | 显示全部楼层


目前深圳有个PE的缺
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