AMD 内部推荐

chrisyl

AMD 招聘，需求多多，附上部分JD，欢迎来投, amdhire@163.com

Location	Job Title
Shanghai	1. PMTS/SMTS/MTS/Sr. Silicon Design Engineering  - PD
	2. Manager/Sr.Manager at Physical Design
	3. PMTS/SMTS/MTS/Sr Silicon Design Engineering  - DV
	1. SMTS/MTS Silicon Design Engineering - PD
	2. Front-End Engineer - Graphics
	3. MTS Silicon Design Engineering – GMHUB Feint
	4. Senior Silicon Design Engineer
	5. Sr. Manager ASIC Design
	6. SMTS Silicon Design Engineer
	7. SMTS/ MTS GFX FE tile owner
	8. SMTS/MTS Silicon Design Engineering -  Feint
	9. MTS Design Verification Engineer (Low power) Urgent
	10. SMTS Silicon Design Engineer (Graphics  performance Analysis & Architecture Modeling)
	11. Intern- GPU infrastructure Urgent
	12. Intern - GFX micro Code design and  functional verification
	1. Sr./ MTS Firmware Engineer - Multi Media  (Diagnostics Team)
	2. MTS/SMTS Design Engineer (FCH Team)
	3. PMTS/Fellow USB IP Arichtect (FCH  Team) Urgent
	4. SMTS IP Design Engineer (NBIO Team)
	5. MTS Silicon support  Engineer (NBIO  Team)
	6. Sr./ MTS IP DV Enineer (CIP Team)
	7. DV Intern (FCH Team)
	8. Sr./ MTS Firmware Engineer - Power  Management ((Diagnostics Team)
	9. Sr./ MTS Firmware Engineer - I/O related  ((Diagnostics Team)
	10. Sr./ MTS Front-End Intergreation Engineer  (CIP Team)
	11. Software Engineer Intern (NBIO Team)
	1. MTS System Design Debug Engineer
	2. MTS OpenGL Compiler Software  Engineer
	3. Sr Software Engineer(NCG Accepted)
	4. MTS Software Engineer - KMD  & Display
	5. MTS Power Performance Lead Urgent
	6.MTS/Sr Validation Engineer
	7. MTS Silicon Design  Engineer(memory信号完整性)
	8. Sr/MTS DFT Engineer
	9. SMTS/DFT Manager
	1. MTS./Sr IP System Engineer (IOMMU/ISP) Urgent
	2. Manager Hardware Development (Board  Design) Urgent
	3. Sr. Program Manager
	4. SMTS Lead System Engineer Urgent
	5. MTS Power Performance Lead
	6. MTS/Sr. Debug Engineer
	7 Sr/ MTS BIOS Engineer
	8. Validation Engineer Urgent
	9. Power Management Intern
	1. SMTS Product Engineer
	2. PMTS Product Development Engineer
	3. Sr Silicon Design Engineer
	4. MTS Software Development Engineer
	5. Silicon Design Engineer 2
	6. Silicon Design Engineer 2
	7. Silicon Design Engineer 2
	8. MTS Silicon Design Engineer
	8. SMTS Silicon Design Engineer
	10. SMTS Firmware Engineer
	11. MTS Firmware Engineer
	1. Machine Learning/GPU Computing Software  Engineer – Sr. Eng/MTS Eng/SMTS/PMTS
	2. MTS Software Engineer – Virtualization
	3. Camera Driver MTS Software Engineer -  Windows
	4. ADAS/Automotive MTS Software Engineer –  Linux BSP/Virtualization
	5. ASIC IC Design SMTS Engineer of ISP
	6. Feint MTS/SMTS Engineer
	7. Linux Kernel MTS Engineer of Machine  Learning/GPU Computing
	1. Solution Architect
Beijing	1. MTS ASIC Verification Engineer – AI &  HPC SoC
	1. PMTS/SMTS/MTS/Sr Machine/ Deep Learning  Software engineer   Urgent
	2. MTS Silicon Design Engineering - PD
	1. Sr. Silicon Design-Physical Design
Hefei	1.  MTS Customer Quality Engineer
Shenzhen	1. Solution Architect
	1. MTS Supplier Quality Engineering
Suzhou	1. Java Engineer
	2. Sr. Supply Chain Specialist
	3. Sr. Planner, Supply Chain
	4. MTS Packaging Engineer-Vendor Management
	5. MTS Quality Engineer
	6. Director Test Manufacturing Engineering
	7. System Level Testing Engineer
Wuhan	1. Sr Software Engineer AE
Chongqing	1. MTS Customer Quality Engineer

1.    Sr. Silicon Design Engineer-Physical Design(Beijing)

Work with globalFront-End design team and physical design team for large scale ASIC GPU chipsimplementation. Focus on RTLàSynthesisàphysical design methodologyoptimize/update to improve fullchip Power/Performance/Area (PPA), includingblock level (full chip)  RTLà Syn àplace&route iteration/optimizing.The individual is expected to be an expert in multiple aspects in Front-End orPD areas, should have strong RTL coding experience or Synthesis or PDknowledge, at least one of these three areas. The individual will providetechnically leadership to the engineering team. The individual is also expectedto be accountable for project delivery.

Job Requirement:

• MSEE     with 2+ years or Bachelor with 5+ years of industrial experience in ASIC     design
  
• 2+     years or more years of experience in RTL coding or DV or Synthesis-PD in     digital ASIC chips
  
• Familiar     with Front-End EDA tools
  
• Familiar     with Back-End (physical design) EDA tools is a plus
  
• Hands     on experience in large scale ASIC chip physical design
  
• Knowledgeable     in all aspects of deep submicron ASIC design flow
  
• Successfully     gone through several complete product development cycles
  
• Demonstrate     strong leadership and work well with cross-functional teams
  
• Good     listening, writing and speaking English
  
• Good     communication skills, strong interpersonal skills and the flexibility
  
• Dedicated,     hardworking and good team player
  
• Familiar     with Unix/Linux environment and good at scripts
  

2.    MTS. Silicon Design Engineer-Physical Design(Beijing)

Job Requirement:

• MSEE     with 6+ years or Bachelor with 9+ years of industrial experience in ASIC     design
  
• 3+     years or more experience in Synthesis-PD in digital ASIC chips
  
• Familiar     with Back-End (physical design) EDA tools
  
• Hands     on experience in large scale ASIC chip physical design
  
• Knowledgeable     in all aspects of deep submicron ASIC design flow
  
• Successfully     gone through several complete product development cycles
  
• Demonstrate     strong leadership and work well with cross-functional teams
  
• Good     listening, writing and speaking English
  
• Good     communication skills, strong interpersonal skills and the flexibility
  
• Dedicated,     hardworking and good team player
  
• Familiar     with Unix/Linux environment and good at scripts
  

3.    SoC DesignVerification Senior Engineer (Beijing)

Beijing GPU SOC team is looking for DV engineers who will work ondesign verification of cutting edge AI/HPC GPU projects, to cover the SOC levelfeature including data-path and interrupt, virtualization, security, powermanagement, etc.

RESPONSIBILITIES:

·      Interface with global architecture and designteams, understand graphics SoC design and feature set

·      SoC DV test bench and infrastructuredevelopment and maintenance

·      Create and execute SoC test plan includingdata-path, virtualization, security, power management, etc.

·      Implement directed and random test cases andTB in C++/UVM, as well as checkers and assertions

·      Support integration and qualification of allthe IPs for SoC

·      Help to improve DV environment building flow

REQUIREMENTS:

·      Master degree in EE/CS with at least 5 years’experience, or Bachelor degree with at least 8 years’ experience in IC orsemiconductor industry.

·      Rich experience of complex ASIC DV flow fromplan to coverage

·      knowledgeable in C++ & SV, familiar withscript languages like Ruby/Perl/Makefile…

·      Strong problem solving, communication andanalytical thinking skills

·      Knowledge on computer architecture and PCIedevices is highly preferred

·      Good knowledge on verification methodologieslike UVM is a big plus

·      Experience in power-aware verification is aplus

·      Can provide technical mentoring and guidanceto junior engineers.

4.    MTSCustomer Quality Engineer Chongqing/Hefei

JobDescription

·      Actas “single point of contact” for ODM customers on quality

·      Leadinvestigation of production quality and yield issue at ODM customers toidentify possible root causes and work with AMD functional teams to driveeffective correction actions & preventative measures.

·      Provideaccurate & comprehensive data analysis to tackle integrated issues andguide AMD functional team to speed up problem solving.

·      SupportPLQ to achieve #1 Quality Rankings among key customers determined by customerscorecards.

·      Drivequality-related dedicated and reactive communication.

·      Acknowledgeand drive closure of RMAs, quality-related issues and customer requests

·      Workclosely with ODM sites & AMD functional teams to ensure robust preventiveactions are in place so there is no recurrence of issue

·      OSV(On-site-verification) deployment for major volume sites and HW/SW/FAEallocation to assure the early identification of root causes.

·      CustomerSupport and Internal Feedback to champion “voice of customers” on qualitywithin AMD

·      Activelycommunicate feedback from your customers to AMD functional team

·      Conducttraining at customer sites

Requirements

·      Requiresa BS/MS degree in Electronic Engineering with 5-10 years of related experiencein the areas of semiconductor manufacturing, product engineering, qualityengineering.

·      Mustbe well-organized, self-directed, self-starter, highly motivated, proactiveproblem solver with the ability to get results without owning resources andpossessing direct authority.

·      Experiencein semiconductor manufacturing and qualification processes as well asreliability procedures, semiconductor assembly/packaging and testing.

·      Familiarand experienced with problem-solving methodologies such as 8D or PDCA.

·      Experiencein statistical process control and yield analysis.

5.        MTS Product Engineer-Hefei

RESPONSIBILITIES:

·      BSEE/MSEEwith over 10 years of hardware/Software experience.

·      Notebookand/or Desktop PC motherboard design or debug experience.

·      EitherChipset/Processor developing/supporting experience, or Server andmulti-processor platform experience strongly preferred.

·      Befamiliar with Windbg and assembly code.

·      Experienceon porting Windows Driver.

·      Experienceon porting BIOS a plus.

·      Usingexperience of either PCI-E, USB, SATA, DDR3  & DDR4, LAN or HTanalyzers, or familiar with protocol is a plus.

·      GoodEnglish written and verbal communication skills, including to customers is aplus.

·      Abilityto work in a team environment.

·      SetupRemote debug for oversea Driver Developers.                                                                                                                           

·      Trackingissue status and communicating with customer.                                                                                                                                                                                                                                          

DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOBDESCRIPTION

·      HelpCustomers to resolve Hardware / Firmware / Driver related problem and narrowdown software issue.

·      Helpresolve / narrow down silicon level issues.

·      On-sitesupport customer to resolve issues.

·      Frequentlyoverseas reviews, debug and training activities.

·      Generatepolicies and procedures to enhance the capabilities of the group.

·      Beexternal voice of AMD to outside customers.

·      Providesystem / silicon-level engineering support to OEM customers for both AMD CPUand Chipset.

·      GoodEnglish communication.

6.    IPArchitect PMTS Beijing

Key Responsibilities:

·      Be part of AMD IO IP team, joining IParchitecture work to define host controller IP structure for next generation ofleading-edge super high speed IO, up to 40 Gb/s. Establishes and maintains AMDhigh speed IO technological leadership position.

·      Defines and develops micro-architecture forhost controller design, based on architectural requirement for next generationIO. Leads RTL code development for IP blocks in Verilog HDL and make surefunctional correct and reusable for different product lines.

·      Is responsible for projects or processes ofsignificant strategic or commercial importance and for project/program results

·      Deals with problems requiring cutting edgeapproaches and champions innovation across the organization

·      Provides consultative direction with seniormanagement

·      Makes technical decisions that have asignificant impact on product families, go to market strategies and customersatisfaction

·      Coaches and mentors experienced staff

·      Represents AMD IO team to the outsidetechnical community, partners and vendors

7.    Sr. MTSFirmware Engineer – Shanghai

Be part of the world's most leading graphics accelerator teamdeveloping test applications for the functional and behavior verification ofstate-of-the-art graphics accelerators. This role is responsible for designingand implementing test plans, as well as analyzing and debugging the results.

Candidate should have a minimum of 3~5 years of related experiencein the diagnostic or verification environments with emphasis on ASICsystem-level testing. Please be sure your relevant experience is highlighted onyour resume.

The candidate would be responsible for planning, designing, writing,debugging and optimizing functional and stress tests for Multi Media hardwareIP.

Must be able to work with hardware architects and logic designersto solve functional issues, and customer support engineers to help resolvetesting deficiencies.

KEY RESPONSIBILITIES

·      Lead multimedia IP feature bring-up and validation onboth pre-silicon environment (FPGA, Palladium) and post-silicon system (realASIC and platform)

·      Develop diagnostics software to bring-up and validateASIC features on both pre-silicon environment (FPGA, Palladium) andpost-silicon system (real ASIC and platform)

·      articipate in APU/GPU silicon bring up

·      Identify and help resolve ASIC, board and firmwareissues, provide diagnostics support to external customers and internalengineering teams

REQUIREMENTS

·      B.Sc. or M.Sc. In EE or CS or equivalent is required

·      ood English required – verbal and written

EXPERIENCE AND SKILLS

·      A minimum of 3~5 years of experience on diagnostic,driver or embedded SW development and closely interact with HW/FW designers

·      Strong mix of large-scale software developmentability and hardware understanding

·      Proficient in C/C++ programming

·      Familiar with source controls systems like Perforce,SVN and Git

·      Familiar with Linux, knowledge and experience ofdevice driver or firmware development is required

·      Hands-on experience with any of SoC/board bring up,video encoding/decoding is preferred.

·      Familiar with video processing and enhancementalgorithms

·      Familiar with video CODEC(decode/encode), HEVC,H.264, VP8/VP9, VC-1, MPEG4,  SVC, AV1 etc.

·      Strong debugging and testing skills

·      Strong communication skills

8.    PMTS.Fellow USB_PCIE IP Architect (FCH Team)

What youdo at AMD changes everything

At AMD, we push the boundaries of what is possible.  We believe in changing the world for thebetter by driving innovation in high-performance computing, graphics, andvisualization technologies – building blocks for gaming, Immersive platforms,and the data center.

Developing great technology takes more than talent: it takesamazing people who understand collaboration, respect, and who will go the“extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the statusquo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we inviteyou to take a look at the opportunities available to come join our team.

Key Responsibilities:

·      Be part of AMD IO IP team, joining IP architecturework to define host controller IP structure for next generation of leading-edgesuper high speed IO, up to 40 Gb/s. Establishes and maintains AMD high speed IOtechnological leadership position.

·      Defines and develops micro-architecture forhost controller design, based on architectural requirement for next generationIO. Leads RTL code development for IP blocks in Verilog HDL and make surefunctional correct and reusable for different product lines.

·      Is responsible for projects or processes ofsignificant strategic or commercial importance and for project/program results

·      Deals with problems requiring cutting edgeapproaches and champions innovation across the organization

·      Provides consultative direction with seniormanagement

·      Makes technical decisions that have asignificant impact on product families, go to market strategies and customersatisfaction

·      Coaches and mentors experienced staff

·      Represents AMD IO team to the outsidetechnical community, partners and vendors

Skills and Experiences:

·       MS degree of EE or CS, with minimum 10 years’ experience

·       Specialized knowledge of USB 3.1/3.2 or Thunderbolt in protocol and linklayers is preferred. Specialized knowledge of PCIE or AMBA is a plus.  

·       Expert of IP micro-architecture and Verilog RTL design on large sizedigital IP.

·       Considered technical leader across project and departmental boundariesand has a proven track record for sustained innovation

·       Fluent English on talking, presentation and writing documents.

·       Work is performed with limited supervision. Strong sense of taskscheduling and deliver on time as predetermined milestones committed tomanager.

·       Can solve complex, novel and non-recurring problems; initiatessignificant changes to existing processes/methods and leads development andimplementation.

llwdahai

好奇一下，为什么一直在不断招人呢？

chrisyl

流动性比较大