【招聘】Cadence 急招多岗位 内推名额 SH/BJ

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A.
Title: Sr/ Lead Application Engineer – Digital Frontend
Location: Shanghai or Beijing

Position Description:
1. To provide key technical support in digital IC design implementation, product demonstration, and sales presentations.
2. To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high performance designs.
3. Have real design experience including synthesis, STA, formal check, DFT, have deep knowledge of low power design concept, CPF/UPF format
4. Assist in technical evaluation, assessment and delivery of concurrent asic/SoC designs.
5. To play a leading role among other team members, while receive little instruction on routine and general assignments.

Position Requirements:
1. A bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications.
2. Ability to understand and articulate technical issues, (and knowledge of) design products and their applications.
3. Requires working knowledge of one or more programming languages, and effective communication and soft skills.
4. An MS degree and/or working experience in multi-nation IC design house is a plus.


B.
Lead/Principal Application Engineer (Front-end Verification)
Location: Beijing

Position Description:
1.Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulation and Acceleration products.
2.Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
3.Train, ramp-up and accompany customer project.
4.Conduct basic and advanced trainings, presentations and demos as necessary.
5.Providing technical expertise to address clients’ queries, which need expert involvement.
6.Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.

Position Requirements:        
1.Over 8 years’ experience in the following areas:
2.Design experience in verilog/Vhdl for IP or SoC chip level.
3.HW verification with knowledge of System Verilog/VHDL and HDL simulators
4. FPGA prototyping project experience
5.Experience with hardware emulator or accelerator is a big advantage
6. Advanced Verification Methodology like UVM is a plus
7. Knowledge of Unix and Linux is highly desired
8.Strong verbal and written communication skills in English
9. Strong teamwork skills with good human relationship


C.
Principal Product Validation Engineer
Location: Beijing

We are in search of a self-motivated and rich experienced Principal Product Validation Engineer to join the Cadence Liberate characterization team.
The Liberate Characterization Suite delivers the industry’s most comprehensive and robust solution for the characterization and validation of customer's foundation IP — from standard cells, I/Os, and complex multi-bit cells, to memories and mixed-signal blocks. Its patented Inside View technology delivers better correlation to silicon by improving library throughput and ensuring timing, power, noise, and statistical coverage of customer's IP.
The successful candidate will help to develop software validation plans to improve the products’ quality, also lead junior PV team members to achieve group test plans. The responsibilities include designing and implementing products test plans, clearly and regularly communicating with management and technical support colleagues, testing and maintaining Liberate products to ensure strong functionality and optimization.

The position are intended for MS or PhD students in EE or CS. The requirements are:
- 5+ years of experience in product validation of EDA software
- Project leading experiences
- Proficient in TCL/Python/Perl/Shell scripts, with good scripting skills
- Ability to work independently and multi-tasks efficiently
- Experiences in Spectre/Hspice circuit simulation, library characterization, static timing analysis and statistics analysis are strong plus


D.
Position: Lead Product Engineer-Spectre
Location:Beijing

Key responsibilities
We are looking for a dynamic individual to join the Spectre/APS development group. The Spectre/APS group has built state-of-the-art simulation technology which is the standard in transistor-level Analog/mixed-signal circuit simulation. The technology is constantly enhanced, and new technologies and features are added to strengthen Spectre/APS’s leading position. As product engineer you will shape our product and contribute to our market success.
As product engineer you are the "voice of the customer" within the Spectre/APS R&D group. You are debugging customer simulation problems, define specifications for new simulation features and bug fixes, work together with R&D on implementation and test, maintain the customer test case suite, support customer evaluations and product roll-out, and are responsible for product documentation, demonstrations and trainings, as well as technical and white papers.

Qualifications
The qualified candidate is required to have strong background in analog/mixed-signal IC design and simulation.
MSEE with 3-5 years’ experience in analog/mixed-signal IC design is required.
Be familiar with common analog/mixed-signal IC designs
Be familiar with customer IC front-end design flow with Cadence tools like virtuoso/ADE/Spectre/APS/AMS is a plus
Knowledge on perl/tcl/csh/python, UNIX, Linux environment is a plus;
Good problem solving skill and team work spirit;
Good English communication skill both verbally and writing;


E.
Title: Lead Program Manager
Location:Beijing

Job Summary:
Cadence Design Systems, Inc. is seeking to hire a Program Manager (PM) based out of the Beijing, China office working on projects involving cross-functional teams focused on development and delivery of world class industry leading software products. The PM will be part of the globally dispersed Program Management Organization (PMO) and will work under guidance of Senior PM leading complex, multi-disciplinary projects. This is an exciting opportunity to be a part of R&D team working on next generation technologies.

Responsibilities:
The new PM will have 2 activities:
-             Tool owner: Propose, define and develop project management tools to improve overall quality and productivity of the PM team and the R&D organization
-             PM: Manage projects and program in an international environment

In this role she/he will:
•            Develop best-in-class WEB-based tools to support our internal Project Management Information System, plugging new technologies into the available tools, as well as developing new ones.
•            Work closely with a variety of people (Marketing, Product Engineering, Development, Validation, Documentation, Project Managers, …) to understand their requirements and drive your WEB development plans
•            Support those teams in using our tools (providing trainings, tutorials, documentation, etc) to provide them with up-to-date and easy-to-use information
•            Actively lead requirements gathering with internal customers to usher projects from early design stage through finished state for delivery to external customers.
•            Monitors product/program/project from initiation through delivery, interfacing with internal or external customer on technical matters.
•            Establish day-to-day operational objectives, organizes interdepartmental activities ensuring completion of the product/program/project on schedule and within budget constraints.
•            Manages change control, priority change. Assesses program issues and areas of risk and takes action to work with internal teams to resolve all problems.
•            Conducts team meetings, documents issues, and proactively keeps stakeholders informed of program status and health.
•            Projects often span offices, time zones and hemispheres, and PM is accountable to keep all the players coordinated on project's progress and deadlines.

Expected qualifications:
•            Strong experience in WEB development: PHP, MySQL, JS, CSS are a MUST. Experience in JS libraries (REACT, JQUERY, etc) and development framework are a PLUS.
•            Good scripting skills (PHP, PERL, Python, CSH…)
•            A BS/MS degree in computer science or related major, with solid experience (3+ years) of the WEB-based development.
•            PM training will be offered
•            Ability to speak and write in English and Chinese fluently and idiomatically.
•            Outstanding interpersonal skills.
•            Be empathetic and enthusiastic.
•            Ability in working with cross-functionally and multi-cultural teams on daily basis.
•            Enjoy problem solving, attention to details and willingness to go above and beyond to chase down loose ends
•            Able and ready to travel to US/Europe 2-3 times per year for internal meetings.
•            Effective written and spoken communication in English is required for day to day interactions with globally dispersed teams.


F.
Title: Lead Product Validation Engineer (STA and timing correlation)
Location: Shanghai

The Position Description is:
1. Identify timing sign-off challenges in complex SOC designs and the correlation issues between preRoute & postroute in advacned process nodes
2. Proactively provide STA & delayCal development suggestions to R&D.
3. Build up STA & delayCal expertise and deliver support to field team and customers whenever needed.
4. Required to acquire expertise and ownership over existing product components as well as develop brand new product features.

The Position Requirements are:
1. Bachelor with 5 years related experience or Master with at least 3 years related experience in design house, FAB or EDA company;
2. Rich experience in IC design flow (front-end or back-end).
3. Experience in advanced nodes designs or knowledge in timing closure is a strong plus.
4. Good Unix System knowledge and script skill of TCL/TK/CSH/PERL.
5. Excellent capability of self-learning, problem solving skills;
6. Being proactive and self-motivated;
7. strong leadership;
8. Good written English and oral English is a strong plus

leviathanist

update new positions

G.
Title: Sr Principal Software Engineer (Location: SH)
Description:

Responsible for development and maintenance of the synthesizer for Palladium.
Implementation for new VHDL/Verilog feature support in synthesizer.
Logic optimization and performance improvement in synthesizer.
Position Requirement:

MS above in CS/EE or similar level of expertise with 5+ years of working experience.
Be skilled in C/C++ programming on Linux platform.
Good team player with strong written and verbal communication skills.
Familiar with VHDL/Verilog and knowledge on EDA tools of simulation, synthesis is required.
Familiar with the distributed computing and database development is preferred.


H.
Title: Lead Software Engineer (Location: SH)
Position Description:

Responsible for development and maintenance of the synthesizer for Palladium.
Implementation for new VHDL/Verilog feature support in synthesizer.
Logic optimization and performance improvement in synthesizer.
Position Requirement:

MS above in CS/EE or similar level of expertise with 5+ years of working experience.
Be skilled in C/C++ programming on Linux platform.
Good team player with strong written and verbal communication skills.
Familiar with VHDL/Verilog and knowledge on EDA tools of simulation, synthesis is required.
Familiar with the distributed computing and database development is preferred.

leviathanist

add SH/BJ positions

I.
Title: Lead Verification Engineer (数字前端验证)
Location: SH

           Position Description:
Deliver/implement advanced verification solutions by utilizing Cadence’s Incisive Verification product portfolio. The engineer should be able to act as a strong team member and contributor, leading  team projects and initiatives. Exercise judgment within generally defined practices and policies.
        Specific duties include:
        Deep understanding on ASIC design and verification flow
        Excellent knowledge of advanced verification methodology like eRM/OVM/UVM/VMM
        Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM)
        Proficiency in System Verilog, System C and/or e (Specman)
        Developing and using Verification Components (eVC,OVC,UVC,VIP)
        Developing and using assertion based verification and formal analysis methods
        Skilled in scripting language, such as Perl,C shell,Python,Makefile
        Assessing the project verification requirements

           Position Requirements:
           Essential Qualifications:
        BS degree with 6+ years of applicable experience, MS degree with 3+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
        Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English.

           Desirable Qualifications:
        Will have demonstrated hands-on experience and expertise with Cadence verification design tools or equivalent tools, flows and methodologies required to execute a verification project.
        Will have demonstrated successful completion of 3+ verification projects as an individual contributor
        Will have DDR project verification experience



J.
Title: Lead Physical Design Engineer (数字后端设计项目方向)
Location: SH

            Position Description:
        Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
        The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation PHY IP physical design, methodology and flow development.

            Position Requirements:        
        BS degree with 5+ years of applicable experience, MS degree with 3+ years of applicable experience in electrical engineering, microelectronics.
        Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.
        Solid knowledge on LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM.
        Successful track records of taping out complex, 16nm/10nm/7nm chips. Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
        Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.



K.
Title: Lead Physical Design Engineer (数字后端设计Research方向)
Location: SH      

•                    Position Description:
        Co-work with the R&D RTL design team for IP architecture exploration and optimization of the design and constraint
        Co-work with other functional teams (Design/STA/Analog/Package/Verification) to optimize the high speed PHY IP development flow and set proper signoff criteria.
        Optimize the physical implementation methodology and flow to meet the tight timing/power target of next generation high speed PHY IP.
        Set and optimize the high speed PHY IP physical implementation guide which will be used by customers and internal global physical implementation teams.   
        Perform physical design implementation tasks including floor planning, place&route, clock tree synthesis and Timing/PV/Power/Signal-EM/CLP/DFM signoff checks for some critical milestone projects.
      

            Position Requirements:        
        BS degree with 6+ years of applicable experience, MS degree with 3+ years of applicable experience in electrical engineering, microelectronics.
        Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.
        Solid knowledge on LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM.
        Successful track records of taping out complex, 16nm/10nm/7nm chips.
        Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
        Innovative, self-motivated, able to work independently or as a team player.
        Excellent verbal and written communication skills in English.



L.
Title: Lead Software Engineer for SPICE
Location: BJ

Position Description:
The position is responsible for designing, implementing and maintaining software and algorithms related to advanced analysis and simulation tools used in the development of VLSI circuits and RF communication systems. The engineer will be responsible for leading multiple development efforts through the complete design cycle and working with a cross-functional team to ensure the software is tested, integrated and documented.

Position Requirements:
•        Skilled in C++ programming, familiar with development under Linux/Unix environment;
•        Good English communication skills both verbal and written
•        Good problem solving skill and ability to work in a team environment
•        Educational requirement is an MS or above in electrical, mechanical, or computer engineering; computer science, or applied mathematics. Candidate should have exposure to and interest in algorithmically-intensive software development.
•        Background in one or more of the following areas is highly desirable:  VLSI circuit simulation, computational electromagnetics, parallel numerical algorithms, spectral methods for solution of ordinary and partial differential equations, numerical linear algebra, computational fluid mechanics, finite element analysis, computational mechanics.



M.
Title: Lead Software Engineer for RF Simulator
Location: BJ

The position is responsible for designing, implementing and maintaining software and algorithms related to advanced analysis and simulation tools used in the development of VLSI circuits and RF communication systems. The engineer will be responsible for leading multiple development efforts through the complete design cycle and working with across-functional team to ensure the software is tested, integrated and documented.
Position Requirements:
•        Skilled in C++ programming, familiar with development under Linux/Unix environment;
•        Good English communication skills both verbal and written
•        Good problem solving skill and ability to work in a team environment
•        Educational requirement is an MS or above in electrical, mechanical, or computer engineering; computer science, or applied mathematics.  Candidate should have exposure to and interest in algorithmically-intensive software development.
•        Background in one or more of the following areas is highlydesirable:  VLSI circuit simulation, computational electromagnetics,parallel numerical algorithms, spectral methods for solution of ordinaryand partial differential equations, numerical linear algebra,computational fluid mechanics, finite element analysis, computational mechanics.
•        Exposure to analog, RF or microwave circuit fundamentals is a strong plus.



N.
Title: Principle Software Engineer
Location: BJ

•        Familiar with Spice language and analog circuit simulation technology.
•        Skilled in C++ programming and development under Linux environment.Analog circuit or digital simulator development experience is a plus
•        Analog circuit design experience is a plus
•        Good mathematics background & knowledge is a plus.
•        EE or CS Master degree with at least 2 years related working experience or above



O.
Title:Software Engineer
Location: BJ

Position Description:
Develop, enhance and maintain digital mixed signal simulator which supports the co-sim between different HDL languages, such as Verilog, VHDL, SystemVerilog, etc, with some direction from manager or senior engineers
Position Requirements:
1. Familiar with Verilog, VHDL, SystemVerilog language
2. Analog circuit or digital simulator development experiences
3. Skilled in C/C++ programming, familiar with development under Linux/Unix environment.
4. Being familiar with Real number modeling is a plus
5. Being familiar with Digital Mixed-signal design is a plus
6. Being familiar with low power design is a plus

leviathanist

Still open

leviathanist

Still open