马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
本帖最后由 小芯 于 2020-1-6 09:48 编辑
坐标上海张江，岗位和公司介绍如下，欢迎有兴趣人士投递简历至 Amanda.Wu@verisilicon.com
，并标明意向岗位。
岗位介绍
1.Engineer/Sr. Engineer of SoC Design 前端设计工程师/高级工程师
2.Sr.Engineer/Staff Engineer of SoC Verification 前端验证高级工程师/资深工程师
3.Engineer/Sr.Engineer of SoC FE Flow 前端流程工程师/高级工程师
1.Engineer/Sr. Engineer of SoC Design Responsibilities:
1.Play animportant role in defining chip spec and devising chip architecture.
2.Develop challenging modules including modulespec definition, macro architecture design, RTL coding, simulation andsynthesis. 3.Carry out chiplevel verification or chip integration/implementation.
4.Help juniorengineers to solve technical issues.
5.Supportcustomers regarding chip applications.
Requirements:
1.Bachelor degreeor above in EE, 3+ years experience.
2.Goodknowledge of some of the following general IP: CPU/DSP, AMBA, DDR/SDRAM, video(HEVC, MIPI…), parallel/serial peripheral module, DMA, interrupt, timer, GPIO.
3.Good skill inthe field of digital circuit design, whole digital design flow and EDA tools;
4.Key member inat least one successfully silicon proven challenging project.
5.Fluent in bothEnglish and Chinese.
6.Self motivated,good communication skill and team work spirit.
2.Sr. Engineer/Staff Engineer of SoC Verification
Responsibilities:
1.Understandingthe expected functionality of designs.
2.Developingtesting and regression plans.
3.Designing anddeveloping verification environment.
4.Running RTL andgate-level simulations/regression.
5.Code/functionalcoverage development, analysis and closure.
Requirements:
1.Minimum of 3 years design/verificationexperience (test plan, test bench, assertions, debugging designs, code coverageetc.).
2.Knowledge inASIC/FPGA design process and verification tools/env ( UVM/OVM…)
3.Familiar withdesign and verification languages (Verilog, System Verilog, SVA etc.).
4.Scripting andautomation skills (tcl, perl, makefile etc) a plus.
5.Familiar withC/C++.
6.Knowledge of DDR/Video/ARM/USB/PCIE , Low PowerVerification with UPF and design experience is a plus.
7.Experiencein CPU/DSP verification, including test plan and test bench development, testcase development and test coverage assessment. and Knowledge of computerarchitecture and micro-architecture (pipeline, out-of-order, cache) is a plus.
8.Additional qualifications include: Good ICverification skills and basic knowledge of logic or circuit design, goodcommunication and problem solving skills.
9.Independent andself-managing.
3.Engineer/Sr.Engineer of SoC FE Flow
Responsibilities:
1.Comprehend the SoC clock structure and workingmode and prepare the SDC file for SoC design.
2.Prepare the DFTplan for the SoC design.
3.SCAN/MBIST/BSD insertion and synthesizemethodology for Flatten / Hierarchical design.
4.Pre/Postsimulation for test patterns.
5.Cooperate withtiming engineer for timing signoff (STA).
6.Analog IP testimplementation and simulation.
7.Support ATE engineer for chip testing debug, andanalyze ATE log file to locate root cause of failure.
8.Formal check ofRTL and netlist.
Requirements:
1.Bachelor'sdegree or above, major in EE, CS or relevant.
2.Above 5years work experience to the one withBachelor's degree and above 3years with Master's degree is required for SeniorEngineer position.
3.Skilled in SoCPPA, better for low power design.
4.Improve lowtest coverage to achieve higher coverage.
5.Skilled incsh/perl/tcl scripts.
6.Be familiarwith concept of SoC and P&R physical implementation.
7.Fluent in bothEnglish and Chinese.
8.Good team workspirit.
| 
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2019-1-10 09:34:37
楼主