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Job Responsibilities:
• Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
• Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.
Job Requirements:
• MS degree of EE.
• Familiar with Verilog RTL design and has experience of large digital ASIC project.
• Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde)
• Familiar with unix/linux and scripts (tcl, perl etc.)
• Fluent English on talking, presentation and writing documents.
• Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
需要不同级别的工程师 最低本科二年经验或者硕士学历 地点上海或者北京
年前面试年后入职 不影响年终奖
公司内部推荐，成功率会高些哦。大家都是工程师，对工作的切入点也会更准确，并且可以指导简历修整，突出个人优势，让个人特长和职位需求更好的match，实现共赢哟。有兴趣的童鞋们可以把简历直接发邮件到我的邮箱 : amdgreaterchina@163.com或者加我微信ic_greaterchina QQ1216517563 有任何关于这边面试、公司文化、工作环境、职业发展的问题都欢迎交流，希望能有效提高你应聘的目的性和面试的成功几率，更希望你能赢得能发挥你个人优势的职位. |
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发表于 2018-12-11 19:09:08
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