成都芯片设计验证职位招聘

daisyyang

成都芯片设计验证职位招聘，有兴趣欢迎联系我了解详情，微信18163979512，邮箱daisy@hibohr.com

芯片设计工程师
工作描述：
-        熟悉Verilog/SystemVerilog设计语言，进行SoC系统级集成工作，包括时钟，复位设计等。
-        根据设定的芯片构架，细化设计方案，编写设计手册，独立完成RTL详细设计，以及模块级验证任务
-        熟练使用主流EDA设计仿真工具，熟悉Perl, Tcl 等基本的脚本编程
-        能够承担或协助FPGA原型验证工作
-        能够进行基本的逻辑综合以及静态时序分析

职位需求：
-        三年以上芯片设计工作经验，至少一次成功流片经验。
-        微电子、计算机、通信工程等相关专业硕士以上学历
-        有音频芯片开发经验者优先。
-        有DFT设计经验者优先
-        熟悉低功耗设计者优先
-        有数字信号处理类芯片开发经验者优先
-        良好的团队合作精神，较强的沟通能力
芯片验证工程师
Job Tasks
?Work with designer to get a full deep insight on the design and develop stressful test plan for SoC and IPs
?Build test bench and create testcase to ensure maximum coverage
?Run simulation in both RTL and netlist level, debug and fix issues, create test reports.
?Develop verification IP which can be reused at different level verification
?Co-work with FPGA engineer to prepare test vector, support test and debug
?SoC system performance profiling, system stress test
?Explore advanced verification methodology, optimize the verification process/environment to improve efficiency and quality
?Support DV manager to do the verification quality control and sign-off the DV task

Qualifications
Must Have
?MSEE/MSCS degree or equivalent
?3-8 years’ experience in design verification field
?Good knowledge in SystemVerilog, C/C++ and UVM
?Good knowledge in the SoC architecture, AXI/AHB protocol. Experienced in full chip verification plan, execution and sign-off.
?Experienced in system performance test
?Strong communications skills and capability
?Self-motivated and good team player

Nice to have
?Strong Programming in Perl, Python
?Good digital signal processing background and be familiar with video processing algorithm, be familiar with MATLAB
?Experienced in low power verification
?Be familiar with FPGA debug.