美资上市公司Synaptics招聘Senior Design Verification Engineer(上海)

caoshangfei

美国上市Fabless公司，上海浦西主要为AE和SE，上海浦东分公司在张江高科地铁站旁。

公司主要产品是指纹识别，IoT，人机交互芯片。

      有兴趣的同学请投递到我的邮箱：wxiangwei@sina.cn。
      详细介绍https://www.moseeker.com/position/index/pid/1914865职位描述

Job Tasks

•        Work with designer to get a full deep insight on the design and develop stressful test plan

•        Build test bench and create testcase to ensure test coverage

•        Run simulation in both RTL and netlist level, debug and fix issues, create test reports

•        Run regression test for each design(RTL/Netlist) update

•        Develop verification IP which can be reused at different level verification

•        Co-work with FPGA engineer to prepare test vector, support test and debug

任职条件

Qualifications

Must Have

•        MSEE/MSCS degree or equivalent

•        Minimum 3 years’ experience in design verification filed

•        Strong working knowledge in SystemVerilog, C and UVM, experienced in DPI integration

•        Experienced in building test benches, checkers, test vectors, assertions, coverage analysis

•        Experienced in SoC verification and debug, be familiar with ARM processor and AXI/AHB protocol

•        Strong communications skill and capability

•        Self-motivated and good team player

Nice to have

•        Strong Programming in Perl, Python

•        Be familiar with FPGA debug

•        Good digital signal processing background and be familiar with video processing algorithm, be familiar with MATLAB

职位要求

• 学历要求：硕士及以上
• 工作经验：5年以上
• 外语要求：熟练

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