Sr. or Front End Design Engineer

RecruiterAMD

有兴趣的朋友请发简历至nina.zhang@amd.com

邮件标题： 姓名+应聘职位+eetop, 谢谢

RESPONSIBILITIES:

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Understand thearchitecture of the graphics IP and functional block being designed

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Build C/C++ model forsimulation

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Build test bench andmonitors for DUT

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Compose test plan andvalidation vectors to ensure functional completeness

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Debugfunction/performance bugs of graphics IP

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Work with globalFront-End design team and physical design team for large scale ASIC chipphysical implementation

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Focus on physicaldesign of deep sub-micron GPU chips including block level (full chip) floorplanning, timing closure, place&route, physical verification etc

REQUIREMENTS:

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Have in depthknowledge of entire design process from Design specification, definingarchitecture, micro-architecture, RTL design and functional verification,synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.

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Have hands-onexperience in Chiplevel Design/Integration activities.

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Some Physical Designexposure required.

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Perform Synthesis andnetlisting tasks such as SDC Development, Scan Insertion, ECO implementation,Formal Verification, etc.

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Some exposure to DFTis a strong plus.

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Work with PhysicalDesign team on Floor Plan, budgeting, timing closure, Signal Integrity, ECOflows, Power analysis, IO PAD placement, etc.

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Should have expertisein: Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC. Goodknowledge of datapath compilers is required.

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Expertise in Perl andTcl is a must.

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Knowledge of chip businterfaces such as AHB and various standard peripherals & interfaces is a plus.

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Should be able to workclosely with RTL Designers and Backend Physical Design teams across multiplesites.

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Must have goodcommunication & Analytical thinking skills.

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Should haveproficiency in flow development and scripting.

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Should be able to Leada team, and provide Technical mentoring and guidance to junior engineers.

EDUCATION:

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Master with at least 5years or Bachelor with at least 8 years working experience in ASIC area